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ltc3883/LTC3883-1 1 3883f n pmbus/i 2 c compliant serial interface C telemetry read-back includes v in , i in , v out , i out , temperature and faults C programmable voltage, current limit, digital soft-start/stop, sequencing, margining, ov/uv/oc and frequency synchronization (250 khz to 1mhz) n 0.5% output v oltage accuracy over temperature n integrated 16-bit adc and 12-bit dac n integrated high side current sense amplifier n internal eeprom and fault logging n integrated n-channel mosfet gate drivers power conversion n wide v in range: 4.5v to 24v n v out range: 0.5v to 5.5v n analog current mode control loop n accurate polyphase ? current sharing for up to 6 phases n auto calibration of inductor dcr n available in a 32-lead (5mm 5mm) qfn package typical a pplica t ion descrip t ion single phase step-down dc/dc controller with digital power system management the lt c ? 3883/LTC3883-1 are polyphase capable dc/dc synchronous step-down switching regulator controllers with a pmbus compliant serial interface. the controllers use a constant frequency, current mode architecture that is supported by the ltpowerplay? software development tool with graphical user interface (gui). switching frequency, output voltage, and device address can be programmed using external configuration resistors. additionally, parameters can be set via the digital interface or stored in on-chip eeprom. the ltc3883/LTC3883-1 can be configured for burst mode ? operation, discontinuous ( pulse- skipping) mode or continuous inductor current mode. the ltc3883 incorpo- rates an internal 5 v linear regulator while the LTC3883-1 uses an external 5v supply for minimum power loss. the ltc3883/LTC3883-1 are available in a 32-lead 5mm 5mm qfn package. fea t ures a pplica t ions n high current distributed power systems n telecom systems n intelligent energy efficient power regulation l, lt , lt c , lt m , opti-loop, polyphase, burst mode, module, linear technology and the linear logo are registered trademarks and ltpowerplay, no r sense and ultrafast are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 5408150, 6580258, 6304066, 7420359, patent pending. load current (a) 0.01 0 efficiency (%) power loss (w) 10 30 40 50 100 70 0.1 1 3883 ta01b 20 80 90 60 0 2 8 7 1 4 6 5 3 10 100 v in = 12v v out = 1.8v f sw = 350khz efficiency and power loss vs load current 0.1f 1f 10f c out 530f pmbus interface to/from other ltc devices write protect 2200pf *some details omitted for clarity mmbt3906 10f 5m 100 d1 m1 m2 1.4k v out 1.8v 20a 4.99k 10nf 0.22f 1f 22f 0.56h tg bg boost sw i in_sns v in_sns v in intv cc ltc3883* tsns share_clk wp sgnd sda scl alert run gpio pgood v dd33 v dd25 i th i sense + v sense i sense ? v in 6v to 24v fault management 1f 1f 3883 ta01a 100
ltc3883/LTC3883-1 2 3883f table o f c on t en t s features ..................................................... 1 applications ................................................ 1 t ypical application ........................................ 1 description .................................................. 1 table of contents .......................................... 2 absolute maximum ratings .............................. 4 pin configuration .......................................... 4 order information .......................................... 4 electrical characteristics ................................. 5 t ypical performance characteristics ................... 9 pin functions .............................................. 12 block diagram ............................................. 14 operation ................................................... 15 overview ................................................................. 15 m ain control loop .................................................. 15 e eprom ................................................................. 16 pow er up and initialization ..................................... 16 s oft-start ................................................................ 17 se quencing ............................................................. 17 v oltage-based sequencing ..................................... 18 sh utdown ............................................................... 18 l ight load current operation ................................. 19 s witching frequency and phase ............................. 19 o utput voltage sensing .......................................... 20 o utput current sensing .......................................... 20 a uto calibration ..................................................... 20 a ccurate dcr temperature compensation ............ 20 i nput current sensing ............................................. 20 l oad sharing .......................................................... 21 e xternal/internal temperature sense ...................... 21 r config (resistor configuration) pins .................. 22 f ault detection and handling .................................. 23 cr c failure ........................................................ 24 s erial interface ....................................................... 24 c ommunication failure ...................................... 24 de vice addressing .................................................. 24 r esponses to v out and i out faults ........................ 25 o utput overvoltage fault response ................... 25 o utput undervoltage response ......................... 25 p eak output overcurrent fault response ........... 25 r esponses to timing faults .................................... 26 r esponses to v in ov faults .................................... 26 r esponses to ot/ut faults ..................................... 26 o vertemperature fault responseinternal ...... 26 o vertemperature and undertemperature fault responseexternals ............................... 26 r esponses to input overcurrent and output undercurrent faults ................................................ 27 r esponses to external faults ................................. 27 f ault logging .......................................................... 27 b us timeout failure ................................................ 27 s imilarity between pmbus, smbus and i 2 c 2-wire interface ...................................................... 27 pm bus serial digital interface ................................ 28 pmbus command summary ............................ 31 pmbus commands ................................................. 31 * data format .......................................................... 36 applications information ................................ 37 c urrent limit programming .................................... 37 i sense + and i sense C pins ......................................... 37 lo w value resistor current sensing ....................... 38 i nductor dcr current sensing ................................ 39 sl ope compensation and inductor peak current .... 40 i nductor value calculation ...................................... 40 i nductor core selection .......................................... 41 p ower mosfet and schottky diode (optional) selection ................................................................. 41 v ariable delay time, soft-start and output voltage ramping ................................................................. 42 d igital servo mode ................................................. 43 s oft off (sequenced off) ........................................ 43 in tv cc regulator .................................................... 44
ltc3883/LTC3883-1 3 3883f table o f c on t en t s topside mosfet driver supply (c b , d b ) ................ 45 un dervoltage lockout ............................................. 45 c in and c out selection ........................................... 45 f ault conditions ...................................................... 46 o pen-drain pins ..................................................... 47 p hase-locked loop and frequency synchronization ...................................................... 47 mi nimum on-time considerations .......................... 48 input current sense amplifier ................................. 48 r config (external resistor configuration pins) ................................................. 49 v oltage selection ................................................ 49 f requency and phase selection using rconfig ............................................................ 51 a ddress selection using rconfig ..................... 51 e fficiency considerations ....................................... 52 c hecking transient response ................................. 52 p olyphase configuration .................................... 53 p c board layout checklist ..................................... 54 pc b oard layout debugging ................................... 56 d esign example ...................................................... 56 c onnecting the usb to i 2 c/smbus/pmbus controller to the ltc3883 in system ...................... 58 i nductor dcr auto calibration ............................... 59 a ccurate dcr temperature compensation ............. 60 l tpowerplay: an interactive gui for digital power .......................................................... 61 p mbus communication and command processing 61 pmbus command details ............................... 64 ad dressing and write protect ................................. 64 g eneral configuration registers ............................. 65 o n/off/margin ........................................................ 66 p wm configuration ................................................ 68 vo ltage .................................................................... 70 i nput voltage and limits ..................................... 70 o utput voltage and limits .................................. 71 c urrent .................................................................... 74 o utput current calibration ................................. 74 o utput current .................................................... 76 i nput current calibration ................................... 77 i nput current ...................................................... 78 te mperature ............................................................ 78 e xternal temperature calibration ........................ 78 external temperature limits ............................... 79 t iming .................................................................... 80 t imingon sequence/ramp ............................. 80 t imingoff sequence/ramp ............................ 81 p recondition for restart ..................................... 81 fa ult response ....................................................... 82 fa ult responses all faults .................................. 82 f ault responses input voltage ........................... 82 f ault responses output voltage ......................... 83 f ault responses output current ......................... 85 f ault responses ic temperature ........................ 86 f ault responses external temperature ............... 87 f ault sharing ........................................................... 88 f ault sharing propagation .................................. 88 f ault sharing response ...................................... 90 s cratchpad ............................................................. 90 i dentification ........................................................... 91 f ault warning and status ........................................ 92 t elemetry ................................................................ 98 n vm memory commands .................................... 10 1 store/restore ................................................... 10 1 fault logging .................................................... 10 2 block memory write/read ................................ 105 typical applications .................................... 107 package description ................................... 111 t ypical application ..................................... 112 related parts ............................................ 112
ltc3883/LTC3883-1 4 3883f v in , sw ...................................................... C0. 3 v to 28 v topside driver voltage (boost) ................ C 0.3 v to 34 v switch transient voltage (sw) ..................... C5 v to 28 v extv cc , intv cc , bg , (boost C sw) ......... C 0.3 v to 6v v sense + , i sense + ........................................... C0.3 v to 6v run , sda , scl , alert ............................. C 0.3 v to 5.5 v freq _ cfg , v out _ cfg , v trim _ cfg , asel , v dd 25 ............................................ C0. 3 v to 2.75 v o r d er i n f orma t ion lead free finish tape and reel part marking* package description temperature range ltc3883euh#pbf ltc3883euh#trpbf 3883 32-lead (5mm 5mm) plastic qfn C40c to 105c ltc3883iuh#pbf ltc3883iuh#trpbf 3883 32-lead (5mm 5mm) plastic qfn C40c to 125c ltc3883euh-1#pbf ltc3883euh-1#trpbf 38831 32-lead (5mm 5mm) plastic qfn C40c to 105c ltc3883iuh-1#pbf ltc3883iuh-1#trpbf 38831 32-lead (5mm 5mm) plastic qfn C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ a bsolu t e m aximum r a t ings ltc3883 LTC3883-1 32 31 30 29 28 27 26 25 9 10 11 12 top view 33 gnd uh package 32-lead (5mm 5mm) plastic qfn 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1v in_sns i in_sns i sense + i sense ? sync scl sda alert boost tg sw v dd33 share_clk wp v dd25 v trim_cfg tsns v sense ? v sense + i th v in intv cc bg pgnd gpio pgood run dnc asel freq_cfg v out_cfg dnc t jmax = 125c, ja = 44c/w, jc = 7.3c/w exposed pad (pin 33) is gnd, must be soldered to pcb 32 31 30 29 28 27 26 25 9 10 11 12 top view 33 gnd uh package 32-lead (5mm 5mm) plastic qfn 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1v in_sns i in_sns i sense + i sense ? sync scl sda alert boost tg sw v dd33 share_clk wp v dd25 v trim_cfg tsns v sense ? v sense + i th v in extv cc bg pgnd gpio pgood run dnc asel freq_cfg v out_cfg dnc t jmax = 125c, ja = 44c/w, jc = 7.3c/w exposed pad (pin 33) is gnd, must be soldered to pcb p in c on f igura t ion (note 1) (v in _ sns C v in ), ( v in C i in _ sns ) ................ C0. 3 v to 0.3 v pgood , gpio , share _ clk , i th , v dd 33 , wp ................................................ C0. 3 v to 3.6 v intv cc peak output current ................................ 10 0 ma operating junction temperature range ( notes 2, 15) .......................................... C 40 c to 125 c storage temperature range .................. C 65 c to 125 c
ltc3883/LTC3883-1 5 3883f e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v, v run = 3.3v, f sync = 500khz (externally driven) unless otherwise specified. symbol parameter conditions min typ max units input voltage v in input voltage range (note 12) l 4.5 24 v i q input voltage supply current normal operation (note 14) v run = 3.3v, no caps on tg and bg v run = 0v 30 20 ma ma v uvlo undervoltage lockout threshold when v in > 4.2v v intvcc /v extvcc falling v intvcc /v extvcc rising 3.7 3.95 v v control loop v outr0 full-scale voltage range 0 set point accuracy (0.6v to 5v) resolution lsb step size vout_command = 5.500v (note 9) l l 5.422 C0.5 12 1.375 5.576 0.5 v % bits mv v outr1 full-scale voltage range 1 set point accuracy (0.6v to 2.5v) resolution lsb step size vout_command = 2.75v (note 9) l l 2.711 C0.5 12 0.6875 2.788 0.5 v % bits mv v linereg line regulation 6v < v in < 24v l 0.02 %/v v loadreg load regulation ?v ith = 1.35v C 0.7v ?v ith = 1.35v C 2.0v l l 0.01 C0.01 0.1 C0.1 % % g m error amplifier g m i th =1.22v 3 mmho i isense input current v isense = 5.5v l 1 2 a v senserin v sense input resistance to ground 0v v pin 5.5v 47 k v illimit resolution 3 bits v ilimmax hi range lo range l l 68 44 75 50 82 56 mv mv v ilimmin hi range lo range 37.5 25 mv mv gate driver tg t r t f tg transition time: rise time fall t ime (note 4) c load = 3300pf c load = 3300pf 30 30 ns ns bg t r t f bg transition time: rise time fall time (note 4) c load = 3300pf c load = 3300pf 20 20 ns ns tg/bg t 1d top gate off to bottom gate on delay time (note 4) c load = 3300pf 10 ns bg/tg t 2d bottom gate off to top gate on delay time (note 4) c load = 3300pf 30 ns t on(min) minimum on-time 90 ns ov/uv output voltage supervisor n resolution 8 bits v range0 voltage range range value = 0 1 5.5 v v range1 voltage range range value = 1 0.4 2.7 v v oustp0 step size range value = 0 22 mv v oustp1 step size range value = 1 11 mv v thacc0 threshold accuracy 2v < v out < 5v range value = 0 l 2 % v thacc1 threshold accuracy 0.9v < v out < 2.5v range value = 1 l 2 % t propov1 ov comparator to gpio low time v od = 10% of threshold 35 s t propuv1 uv comparator to gpio low time v od = 10% of threshold 35 s v in voltage supervisor n resolution 8 bits
ltc3883/LTC3883-1 6 3883f e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v, v run = 3.3v, f sync = 500khz (externally driven) unless otherwise specified. symbol parameter conditions min typ max units v inrange full-scale voltage 4.5 20 v v instp step size 82 mv v inthacc threshold accuracy 8.75v < v in < 20v l 2.5 % t propvin comparator response time (vin_on and vin_off) v od = 10% of threshold 100 s output voltage readback n resolution lsb step size 16 244 bits v v f/s full-scale sense voltage (note 10) v run = 0v (note 8) 8 v v out_tue total unadjusted error t j = 25c, v out > 0.6v (note 8) l 0.2 0.5 % % v os zero-code offset voltage l 500 v t convert conversion time (note 6) 90 ms v in voltage readback n resolution (note 5) 10 bits v f/s full-scale input voltage (note 11) 38.91 v v in_tue total unadjusted error t j = 25c, v vin > 4.5v l 0.4 2 % % t convert conversion time (note 6) 90 ms output current readback n resolution lsb step size (note 5) 0v |v isense + C v isense C | 16mv 16mv |v isense + C v isense C | 32mv 32mv |v isense + C v isense C | 64mv 64mv |v isense + C v isense C | 128mv 10 15.26 30.52 61 122 bits v v v v i f/s full-scale input current (note 7) r isense = 1m 128 a i out_tue total unadjusted error (note 8) v isense > 6mv l 1 % v os zero-code offset voltage 28 v t convert conversion time (note 6) 90 ms input current readback n resolution lsb step size ( note 5) 8 x gain, 0v |v in_sns C i in_sns | 8mv 4x gain, 0v |v in_sns C i in_sns | 20mv 2x gain, 0v |v in_sns C i in_sns | 50mv 10 15.26 30.52 61 bits v v v i in_tue total unadjusted error 8x gain, v isense > 2.5mv (note 8) 4x gain, v isense > 4mv (note 8) 2x gain, v isense > 6mv (note 8) l l l 1.6 1.3 1.2 % % % v os zero-code offset voltage 50 v t convert conversion time (note 6) 180 ms supply current readback n resolution lsb step size (note 5) 10 122 bits v i chip_tue total unadjusted error (ltc3883 only) total unadjusted error (LTC3883-1 only) l l 5 200 % a t convert conversion time (note 6) 180 ms duty cycle readback d_res resolution (note 5) 10 bits d_tue total unadjusted error 16.3% duty cycle C3 3 % t convert conversion time (note 6) 90 ms
ltc3883/LTC3883-1 7 3883f e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v, v run = 3.3v, f sync = 500khz (externally driven) unless otherwise specified. symbol parameter conditions min typ max units temperature readback (t0, t1) t res_t resolution 0.25 c t0_tue external tsns tue v tsns = 72mv (note 8) l 3 c ti_tue internal tsns tue v run = 0.0v, f sync = 0khz (note 8) 1 c t convert_t update rate (note 6) 90 ms intv cc regulator v intvcc internal v cc voltage no load (ltc3883 only) 6v < v in < 24v l 4.8 5 5.2 v v ldo_int intv cc load regulation (ltc3883 only) i cc = 0ma to 50ma 0.5 2 % v dd33 regulator v dd33 internal v dd33 voltage 4.5v < v intvcc /v extvcc l 3.2 3.3 3.4 v i lim v dd33 current limit v dd33 = gnd, v in = intv cc = 4.5v 100 ma v dd33_ov v dd33 overvoltage threshold 3.5 v v dd33_uv v dd33 undervoltage threshold 3.1 v v dd25 regulator v dd25 internal v dd25 voltage l 2.25 2.5 2.75 v i lim v dd25 current limit v dd25 = gnd, v in = intv cc = 4.5v 80 ma oscillator and phase-locked loop f osc oscillator frequency accuracy 250khz < f sync < 1mhz measured falling edge-to-falling edge of sync with switch_frequency = 250.0.and 1000.0 l 7.5 % v th,sync sync input threshold v clkin falling v clkin rising 1 1.5 v v v ol,sync sync low output voltage i load = 3ma l 0.2 0.4 v i leaksync sync leakage current in slave mode 0v v pin 3.6v 5 a sync- sync to channel phase relationship based on the falling edge of sync and rising edge of tg mfr_pwm_config_ lt c 3883[2:0] = 0 mfr_pwm_config_ lt c 3883[2:0] = 1 mfr_pwm_config_ lt c 3883[2:0] = 2 mfr_pwm_config_ lt c 3883[2:0] = 3 mfr_pwm_config_ lt c 3883[2:0] = 4 mfr_pwm_config_ lt c 3883[2:0] = 5 mfr_pwm_config_ lt c 3883[2:0] = 6 mfr_pwm_config_ lt c 3883[2:0] = 7 0 90 180 270 60 120 240 300 deg deg deg deg deg deg deg deg eeprom characteristics endurance (note 13) 0c < t j < 85c during eeprom write operations l 10,000 cycles retention (note 13) t j < 125c l 10 years mass_write mass write operation time store_user_all, 0c < t j 85c during eeprom write operations l 440 4100 ms digital inputs scl, sda, run, gpio , pgood v ih input high threshold voltage scl, sda, run, gpio, pgood l 2.0 v v il input low threshold voltage scl, sda, run, gpio, pgood l 1.4 v v hyst input hysteresis scl, sda 0.08 v c pin input capacitance 10 pf digital input wp i puwp input pull-up current wp 10 a open-drain outputs scl, sda, gpio, alert, run, share_clk, pgood v ol output low voltage i sink = 3ma l 0.4 v
ltc3883/LTC3883-1 8 3883f e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v, v run = 3.3v, f sync = 500khz (externally driven) unless otherwise specified. symbol parameter conditions min typ max units digital inputs share_clk, wp v ih input high threshold voltage l 1.5 1.8 v v il input low threshold voltage l 0.6 1.0 v leakage current sda, scl, alert, run i ol input leakage current 0v v pin 5.5v l 5 a leakage current gpio , pgood i gl input leakage current 0v v pin 3.6v l 2 a digital filtering of gpio i fltg input digital filtering gpio 3 s digital filtering of run i fltg input digital filtering run 10 s pmbus interface timing characteristics f scl serial bus operating frequency l 10 400 khz t buf bus free time between stop and start l 1.3 s t hd, sta hold time after repeated start condition. after this period, the first clock is generated l 0.6 s t su, sta repeated start condition setup time l 0.6 s t su,sto stop condition setup time l 0.6 s t hd, dat data hold time receiving data transmitting data l l 0 0.3 0.9 s s t su, dat data setup time receiving data l 0.1 s t timeout_smb stuck pmbus timer non-block reads stuck pmbus timer block reads measured from the last pmbus start event 32 150 ms ms t low serial clock low period l 1.3 10000 s t high serial clock high period l 0.6 s note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3883/LTC3883-1 are tested under pulsed load conditions such that t j t a . the ltc3883e/ltc3883e-1 are guaranteed to meet performance specifications from 0 c to 85 c. specifications over the C40c to 105 c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3883i/ltc3883i-1 are guaranteed over the full C40 c to 125 c operating junction temperature range. t j is calculated from the ambient temperature, t a , and power dissipation, p d , according to the following formula: t j = t a + (p d ? ja ) the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to ground unless otherwise specified. note 4: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 5: the data format in pmbus is 5 bits exponent (signed) and 11 bits mantissa (signed). this limits the output resolution to 10 bits though the internal adc is 16 bits and the calculations use 32-bit words. note 6: the data conversion is done in round robin fashion. all inputs signals are continuously converted for a typical latency of 120ms. note 7: the iout_cal_gain = 1.0m and mfr_iout_tc = 0.0. value as read from read_iout in amperes. note 8: part tested with pwm disabled. evaluation in application demonstrates capability. tue (%) = adc gain error (%) + 100 ? [zero code offset + adc linearity error]/actual value. note 9: all v out commands assume the adc is used to auto-zero the output to achieve the stated accuracy. ltc3883 is tested in a feedback loop that servos v out to a specified value. note 10: the maximum v out voltage is 5.5v. note 11: the maximum v in voltage is 28v. note 12: when v in < 6v, intv cc must be tied to v in . note 13: eeprom endurance is guaranteed by design, characterization and correlation with statistical process controls. data retention is production tested via a high temperature bake at wafer level.the minimum retention specification applies for devices whose eeprom has been cycled
ltc3883/LTC3883-1 9 3883f typical p er f ormance c harac t eris t ics load step (burst mode operation) load step (forced continuous mode) load step (pulse-skipping mode) efficiency vs load current, v out = 1.8v (ltc3883) efficiency vs load current, v out = 3.3v (ltc3883) efficiency and power loss vs input voltage (ltc3883) inductor current at light load start-up into a pre-biased load soft-start ramp load current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.01 1 10 100 3883 g01 0 0.1 ccm dcm bm v in = 12v v out = 1.8v f sw = 350khz l = 0.56h dcr = 1.8m v in (v) 5 80 efficiency (%) power loss (w) 82 84 86 88 90 92 1.0 1.5 2.0 2.5 3.0 3.5 4.0 10 15 20 3883 g03 25 run 2v/div v out 1v/div 5ms/div t rise = 10ms t delay = 5ms v out = 2v 3883 g08 forced continuous mode 2a/div burst mode operation 2a/div pulse-skipping mode 2a/div 1s/div v in = 12v v out = 1.8v i load = 100a 3883 g07 run 2v/div v out 1v/div 5ms/div t rise = 10ms t delay = 5ms 3883 g09 load current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.01 1 10 100 3883 g02 0 0.1 ccm dcm bm v in = 12v v out = 3.3v f sw = 350khz l = 0.56h dcr = 1.8m i load 5a/div inductor current 5a/div v out 100mv/div ac-coupled 50s/div v in = 12v v out = 1.8v 0.3a to 5a step 3883 g04 i load 5a/div inductor current 5a/div v out 100mv/div ac-coupled 50s/div v in = 12v v out = 1.8v 0.3a to 5a step 3883 g05 i load 5a/div inductor current 5a/div v out 100mv/div ac-coupled 50s/div v in = 12v v out = 1.8v 0.3a to 5a step 3883 g06 e lec t rical c harac t eris t ics less than the minimum endurance specification. the restore_user_all command (nvm read) is valid over the entire operating temperature range. note 14: the LTC3883-1 quiescent current (i q ) equals the i q of v in plus the i q of extv cc . note 15: the ltc3883 includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability.
ltc3883/LTC3883-1 10 3883f typical p er f ormance c harac t eris t ics soft-off ramp current sense threshold vs i th voltage (low range) maximum current sense threshold vs duty cycle, v out = 0v maximum current sense threshold vs common mode voltage regulated output vs temperature share_clk frequency vs temperature share-clk frequency vs v in quiescent current vs temperature v out measurement error vs v out run 2v/div v out 1v/div 5ms/div t fall = 5ms t delay = 10ms 3883 g10 duty cycle (%) 0 maximum current sense threshold (mv) 51 53 55 90 3883 g12 49 47 50 52 54 48 46 45 30 50 70 50mv sense condition temperature (c) ?50 0.4975 v out (v) 0.4980 0.4990 0.4995 0.5000 0.5025 0.5010 0 50 75 3883 g14 0.4985 0.5015 0.5020 0.5005 ?25 25 100 125 150 temperature (c) ?50 90 share_clk frequency (khz) 95 100 105 110 ?25 0 25 50 3883 g15 75 100 125 150 v in (v) 6 share_clock frequency (khz) 100.0 100.5 22 3883 g16 99.5 99.0 10 14 16 2826 101.0 18 8 12 24 20 temperature (c) ?50 10 quiescent current (ma) 15 20 25 ?25 0 25 50 3883 g17 75 100 125 150 v out (v) 0.5 meassured error (mv) 0.40 0.30 0.20 0.10 0 ?0.10 ?0.20 ?0.30 ?0.40 4.5 3883 g18 1.5 2.5 3.5 5.5 4 1 2 3 5 v ith (v) 0 current limit (a) with 1m sense resistor 10 20 30 1.5 2.5 3883 g11 0 ?10 ?20 0.5 1 2 40 50 60 v sense 50mv v sense 25mv common mode voltage (v) 0 50.0 maximum current sense threshold (mv) 50.5 1 2 3 4 3883 g13 5 51.5 51.0 50mv sense condition
ltc3883/LTC3883-1 11 3883f typical p er f ormance c harac t eris t ics v out command inl v out command dnl intv cc line regulation v out ov threshold vs temperature (1v target) v out ov threshold vs temperature (2v target) v out ov threshold vs temperature (4v target) v out (v) ?1.0 inl (lsbs) 0 1.0 2.0 ?0.5 0.5 1.5 1.5 2.5 3.5 4.5 3883 g19 5.5 10.5 2 3 4 5 v out (v) ?0.3 dnl (lsbs) ?0.1 0.1 0.3 ?0.2 0 0.2 1.5 2.5 3.5 4.5 3883 g20 5.5 10.5 2 3 4 5 v in (v) 5 4.50 4.75 5.25 20 3883 g21 4.25 4.00 10 15 25 3.75 3.50 5.00 intv cc (v) temperature (c) ?50 0.990 1v ov threshold (v) 0.995 1.000 1.005 1.010 ?25 0 25 50 3883 g22 75 100 125 150 temperature (c) ?50 1.97 2v ov threshold (v) 1.98 1.99 2.00 2.01 0 50 100 150 3883 g23 2.02 2.03 ?25 25 75 125 temperature (c) ?50 3.96 4v ov threshold (v) 3.97 3.98 3.99 4.00 0 50 100 150 3883 g24 4.02 4.01 4.03 4.04 ?25 25 75 125 external temperature error vs temperature i out error vs i out room temperature i in error vs i in room temperature temperature (c) ?50 ?1.0 measurement error (c) ?0.8 ?0.4 ?0.2 0 1.0 0.4 0 50 75 3883 g25 ?0.6 0.6 0.8 0.2 ?25 25 100 125 output current (a) 0 measurement error (ma) 0 2 4 20 3883 g26 ?2 ?4 ?8 5 10 15 ?6 8 6 input current (a) 0 measurement error (ma) 0 1 2 3883 g27 ?1 ?2 ?3 1 2 3 4 5 3
ltc3883/LTC3883-1 12 3883f p in func t ions typical p er f ormance c harac t eris t ics dc output current matching in a 2-phase system (ltc3883) total current (a) 0 channel current (a) 15 20 25 15 25 40 3883 g28 10 5 0 5 10 20 30 35 chan 0 chan 1 dynamic current sharing during a load transient in a 2-phase system dynamic current sharing during a load transient in a 2-phase system v in_sns (pin 1): input current sense comparator input. the (C) input to the input current comparator is normally connected to the supply side of the input current sense resistor through a 100 resistor. if the input current sense amplifier is not used, this pin must be shorted to the i in_sns and v in pins. i in_sns (pin 2): input current sense comparator input. the (+) input to the input current comparator is normally connected to the power stage side of the input current sense resistor through a 100 resistor. if the input current sense amplifier is not used, this pin must be shorted to the v in_sns and v in pins. i sense + (pin 3): current sense comparator input. the (+) input to the current comparator is normally connected to the dcr sensing network or current sensing resistor. i sense C (pin 4): current sense comparator input. the (C) input is connected to the output. sync (pin 5): external clock synchronization input and open-drain output pin. if an external clock is present at this pin, the switching frequency will be synchronized to the external clock. if clock master mode is enabled, this pin will pull low at the switching frequency with a 500 ns pulse width to ground. a resistor pull- up to 3.3 v is required in the application. scl (pin 6): serial bus clock input. a pull-up resistor to 3.3v is required in the application. sda (pin 7): serial bus data input and output. a pull-up resistor to 3.3v is required in the application. alert (pin 8): open-drain digital output. connect the smbalert signal to this pin. gpio (pin 9): digital programmable general purpose inputs and outputs. open-drain output. pgood (pin 10): digital power good indicator. open- drain output. run (pin 11): enable run input. logic high on this pin enables the controller. this pin requires a resistor pull- up to 3.3 v in the application and should be driven by an open-drain digital output. dnc (pins 12, 16): do not connect to this pin. asel (pin 13): serial bus address configuration input. connect a 1% resistor divider between the chip v dd25 asel and gnd in order to select the 4 lsbs of the serial bus interface address. a resistor divider on asel is required if there are more than one ltc3883 on the same board to assure the user can independently program each ic. if the pin is left open, the ic will use the value programmed in the nvm. minimize capacitance when the pin is open to assure accurate detection of the pin state. current 5a/div 5s/div v in = 12v v out = 1.8v f sw = 500khz l = 0.4h 15a to 5a load step 3883 g29 current 5a/div 5s/div 3883 g30 v in = 12v v out = 1.8v f sw = 500khz l = 0.4h 5a to 15a load step
ltc3883/LTC3883-1 13 3883f p in func t ions freq_cfg (pin 14): frequency or phase set/select pin. connect a 1% resistor divider between the chip v dd25 freq_cfg and gnd in order to select switching frequency or phase. if the pin is left open, the ic will use the value programmed in the nvm. minimize capacitance when the pin is open to assure accurate detection of the pin state. v out_cfg (pin 15): output voltage select pin. connect a 1% resistor divider between the chip v dd25 , v out_cfg and sgnd in order to select output voltage. this voltage can be adjusted with the v trim_cfg pins. if the pin is left open, the ic will use the value programmed in the nvm. minimize capacitance when the pin is open to assure ac- curate detection of the pin state. v trim_cfg (pin 17): voltage trim select pin. connect a 1% resistor divider between the chip v dd25 , v trim_cfg and sgnd in order to adjust the output voltage set point. the v trim_cfg settings in conjunction with the v out_cfg setting adjusts the voltage set point. if the pin is left open, the ic will either not modify the v out_cfg setting or use nvm. minimize capacitance when the pin is open to assure accurate detection of the pin state. v dd25 (pin 18): internally generated 2.5 v power supply output. bypass this pin to gnd with a low esr 1 f capaci- tor. do not load this pin with external current. wp (pin 19): write protect pin active high. an internal 10a current source pulls the pin to v dd33 . if wp is high, the pmbus writes are restricted. share_clk (pin 20): share clock, bidirectional open- drain clock sharing pin. nominally 100 khz. used to synchronize the timing between multiple ltc3883 s. tie all the share_clk pins together. all ltc3883s will synchronize to the fastest clock. an equivalent pull-up resistance of 5.49k to v dd33 is required. v dd33 (pin 21): internally generated 3.3 v power supply output. bypass this pin to gnd with a low esr 1 f capaci- tor. do not load this pin with external current. sw (pin 22): switch node connection to the inductor. voltage swings at the pins are from a schottky diode (external) voltage drop below ground to v in . tg (pin 23): top gate driver output. this is the output of the floating driver with a voltage swing equal to intv cc superimposed on the switch node voltage. boost (pin 24): boosted floating driver supply. the (+) terminal of the booststrap capacitor connects to this pin. this pin swings from a diode voltage drop below intv cc up to v in + intv cc . pgnd ( pin 25): power ground pin. connect this pin closely to the source of the bottom n-channel mosfet, the (C) terminal of c intvcc and the (C) terminal of c in . bg (pin 26): bottom gate driver output. this pin drives the gates of the bottom n-channel mosfet between pgnd and intv cc . intv cc (pin 27, ltc3883): internal regulator 5 v out- put. the control circuits are powered from this voltage. decouple this pin to pgnd with a minimum of 4.7 f low esr tantalum or ceramic capacitor. extv cc ( pin 27, LTC3883-1): external regulator 5 v input. the control circuits are powered from this voltage. decouple this pin to pgnd with a minimum of 4.7 f low esr tantalum or ceramic capacitor. v in ( pin 28): main input supply. decouple this pin to pgnd with a capacitor (0.1 f to 1 f). for applications where the main input power is 5 v, tie the v in and intv cc pins together. if the input current sense amplifier is not used, this pin must be shorted to the v in_sns and i in_sns pins. i th (pin 29): current control threshold and error ampli- fier compensation node. the current comparator tripping threshold increases with the i th voltage. v sense + (pin 30): positive voltage sense input. v sense C (pin 31): negative voltage sense input. tsns ( pin 32): external diode temperature sense. connect to the anode of a diode-connected pnp transistor and star connect the cathode to gnd in order to sense remote temperature. if an external temperature sense element is not installed, short pin to ground and set the ut _ fault _ limit to C275 c, set the ut_fault_response to ignore, and set iout_cal_gain_tc to 0. gnd ( exposed pad pin 33): ground. all small-signal and compensation components should connect to this ground, which in turn connects to pgnd at one point.
ltc3883/LTC3883-1 14 3883f b lock diagram 16-bit adc pwm1 + ? ? + ? ? + + + + ? ? pwm0 ? + ? + ? + 8:1 mux tmux 2a i lim dac (3 bits) ov 8-bit ov dac 8-bit uv dac 12-bit set point dac uv ea + 0.56v 1.22v burst i th r c c c1 gnd 30a ? + ? + ao r r 9r 2r gnd pwm clock v out_cfg r v sense + tsns v sense ? r switch logic and anti- shoot- through ov run ss uvlo rev uv on fcnt 31 30 32 15 v trim_cfg 17 freq_cfg 14 asel 3883 f01 13 9 11 pgnd c intvcc 25 bg d b m1 intv cc /extv cc v dd33 26 i sense ? 4 i sense + 3 sw 22 tg c b 23 boost 24 v dd33 21 v in c vin 28 1 intv cc /extv cc (LTC3883-1) 27 m2 c out v out + 3.3v subreg 2.5v subreg 5v reg ? + ? + ? + ? + 1 71.1k active clamp uvlo intv cc slope compensation slave v dd33 miso mosiclk master ram sync run 10 pgood gpio eeprom main control program rom v dd33 compare i lim range select hi: 1:1 lo: 1:1.5 3k 38r i in r i cmp i rev 29 33 1 + ? + ? s ref v stby gnd q pwm_clock v in_sns r iinsns r vin v in c in 2 i in_sns r 8-bit v in_on threshold dac phase det v co phase selector clock divider sinc 3 uvlo osc (32mhz) config detect channel timing management 8 7 6 19 wp share_clk scl sda alert pmbus interface (400khz compatible) 20 sync gnd m2 gnd v dd33 5 v dd25 18 v dd25 ltc3883 only 19.5r r + ? + figure 1. block diagram
ltc3883/LTC3883-1 15 3883f o pera t ion o verview th e ltc3883 is a constant frequency, analog current mode controller for dc/dc step-down applications with a digital interface. the ltc3883 digital interface is compatible with pmbus which supports bus speeds of up to 400 khz. a typical application circuit is shown on the first page of this data sheet.major features include: n programmable output v oltage n programmable input v oltage comparator n programmable current limit n programmable switching frequency n programmable ov and uv comparators n programmable on and off delay t imes n programmable output rise/fall t imes n phase - l ocked loop for synchronous, polyphase opera - tion (2, 3, 4 or 6 phases) n input and output voltage/current, temperature and duty cycle t elemetry n fully differential load sense n integrated gate drivers n non-volatile configuration memory n optional e xternal configuration resistors for key operating parameters n optional time-base interconnect for synchronization between multiple controllers n fault logging n wp pin to protect internal configuration n standalone operation after user factory configuration n pmbus, 400khz compliant interface the pmbus interface provides access to important power management data during system operation including: n internal controller temperature n external system temperature via optional diode sense elements n average output current n average pwm duty cycle n average output voltage n average input voltage n average input current n configurable, latched and unlatched individual fault and warning status fault reporting and shutdown behavior are fully configu- rable using the gpio output (gpio ). a dedicated pin for alert is provided. the shutdown operation also allows all faults to be individually masked and can be operated in either unlatched (hiccup) or latched modes. individual status commands enable fault reporting over the serial bus to identify the specific fault event. fault or warning detection includes the following: n output undervoltage/overvoltage n input undervoltage/overvoltage n input and output overcurrent n internal overtemperature n external overtemperature n communication, memor y or logic (cml) fault m ain c ontrol l oop the ltc3883 is a constant frequency, current mode step- down controller that operates at a user-defined relative phasing. during normal operation the top mosfet is turned on when the clock for that channel sets the rs latch, and turned off when the main current comparator, i cmp , resets the rs latch. the peak inductor current at which i cmp resets the rs latch is controlled by the voltage on the i th pin which is the output of the error amplifier, ea. the ea negative terminal is equal to the v sense voltage divided by 5.5 (2.75 if range = 1). the positive terminal of the ea is connected to the output of a 12-bit dac with values ranging from 0 v to 1.024 v. the output voltage, through feedback of the ea, will be regulated to 5.5 times the dac output (2.75 times if range = 1). the dac value is calculated by the part to synthesize the users desired output voltage. the output voltage is programmed by the user either
ltc3883/LTC3883-1 16 3883f o pera t ion with the resistor configuration pins detailed in tables 12 and 13 or by the v out command ( either from nvm or by pmbus command). refer to the pmbus command section of the data sheet or the pmbus specification for more details. the output voltage can be modified by the user at any time with a pmbus vout_command. this command will typically have a latency less than 10ms. the user is encouraged to reference the pmbus power system management protocol specification to understand how to program the ltc3883. this specification can be found at http://www.pmbus.org/specs.html. continuing the basic operation description, the current mode controller will turn off the top gate when the peak current is reached. if the load current increases, v sense will slightly droop with respect to the dac reference. this causes the i th voltage to increase until the average inductor current matches the new load current. after the top mosfet has turned off, the bottom mosfet is turned on. in continuous conduction mode, the bottom mosfet stays on until the end of the switching cycle. eeprom the ltc3883 contains internal eeprom ( nonvolatile memory) to store configuration settings and fault log information. eeprom endurance retention and mass write operation time are specified in the electrical characteristics and absolute maximum ratings sections. write opera- tions above t j = 85 c or below 0 c are possible although the electrical characteristics are not guaranteed and the eeprom will be degraded. read operations performed at temperatures between 85 c and 125 c will not degrade the eeprom. writing to the eeprom above 85 c will result in a degradation of retention characteristics. the fault logging function, which is useful in debugging system problems that may occur at high temperatures, only writes to fault log eeprom locations. if occasional writes to these registers occur above 85 c, the slight degradation in the data retention characteristics of the fault log will not take away from the usefulness of the function. it is recommended that the eeprom not be written when the die temperature is greater than 85 c. if the die temperature exceeds 130 c, the ltc3883 will disable all eeprom write operations. all eeprom write operations will be re-enabled when the die temperature drops below 125c . ( the controller will also disable when the die tem- perature exceeds the internal overtemperature fault limit.) the degradation in eeprom retention for temperatures >125c can be approximated by calculating the dimen- sionless acceleration factor using the following equation: af = e ea k ? ? ? ? ? ? ? 1 t use + 273 ? 1 t stress + 273 ? ? ? ? ? ? ? ? ? ? ? ? ? ? where: af = acceleration factor ea = activation energy = 1.4ev k = 8.617 ? 10 C5 ev/k t use = 125c specified junction temperature t stress = actual junction temperature in c example: calculate the effect on retention when operating at a junction temperature of 135c for 10 hours. t stress = 130c t use = 125c af= e [(1.4/8.617 ? 10 C5 ) ? (1/398 C 1/403)] = 1.66 the equivalent operating time at 125c = 16.6 hours. thus the overall retention of the eeprom was degraded by 16.6 hours as a result of operating at a junction tem- perature of 130 c for 10 hours. the effect of the overstress is negligible when compared to the overall eeprom retention rating of 87,600 hours at a maximum junction temperature of 125c. p ower u p and i nitiali z a tion the ltc3883 is designed to provide standalone supply sequencing and controlled turn-on and turn-off opera- tion. it operates from a single input supply (4.5 v to 24v) while three on-chip linear regulators generate internal 2.5v , 3.3 v and 5 v. if v in is below 6 v, the intv cc and v in pins must be tied together. the controller configuration is initialized by an internal threshold based uvlo where v in must be approximately 4 v and the 5v, 3.3 v and 2.5v linear regulators must be within approximately 20% of the regulated values. the LTC3883-1 does not have an
ltc3883/LTC3883-1 17 3883f o pera t ion internal 5 v linear regulator. the extv cc pin is driven by an external regulator to improve efficiency of the circuit and minimize power on the ltc3883. the extv cc pin must exceed approximately 4 v before the internal uvlo is exceeded. to minimize application power, the extv cc pin can be supplied by a switching regulator. during initialization, the external configuration resistors are identified and/or contents of the nvm are read into the controllers commands and all pwm outputs are in high impedance ( hi-z) mode. the run and gpio pins are held low. the ltc3883 will use the contents of tables 12 to 15 to determine the resistor defined parameters. see the resistor configuration section for more detail. the resistor configuration pins only control some of the preset values of the controller. the remaining values are programmed in nvm either at the factory or by the user. if the configuration resistors are not inserted or if the ignore rconfig bit is asserted (bit 6 of the mfr_config_ all_ lt c 3883 configuration command), the ltc3883 will use only the contents of nvm to determine the dc/dc characteristics. the asel value read at power-up or reset is always respected unless the pin is open. the asel will use the msb from nvm and the lsb from the detected threshold. see the applications information section for more detail. after the part has initialized, an additional comparator monitors v in . the vin_on threshold must be exceeded before the output power sequencing can begin. after v in is initially applied, the part will typically require 130 ms to initialize and begin the ton_delay timer. the readback of voltages and currents may require an additional 120ms. s of t -s t art the part must enter the run state prior to soft-start. the run pin is released by the ltc3883 after the part initializes and v in is greater than the vin_on threshold. if multiple ltc3883s are used in an application, they all hold their respective run pins low until all devices initialize and v in exceeds the vin_on threshold for every device. the share_clk pin assures all the devices connected to the signal use the same time base. the share_clk pin is held low until the part has initialized after v in is applied. the ltc3883 can be set to turn off ( or remain off) if share_ clk is low ( set bit 2 of mfr_chan_config_ltc3883 to a 1). this allows the user to assure synchronization across numerous ltc ics even if the run pins can not be connected together due to board constraints. in general, if the user cares about synchronization between chips it is best to connect all the respective run pins together and to connect all the respective share_clk pins together and pull up to v dd33 with a 10 k resistor. this assures all chips begin sequencing at the same time and use the same time base. after the run pin releases and prior to entering a constant output voltage regulation state, the ltc3883 performs a monotonic initial ramp or soft-start. soft- start is performed by actively regulating the load voltage while digitally ramping the target voltage from 0 v to the commanded voltage set- point. once the ltc3883 is commanded to turn on , ( after power up and initialization) the controller waits for the user specified turn-on delay (ton_delay) prior to initiating this output voltage ramp. the rise time of the voltage ramp can be programmed using the ton_ rise command to minimize inrush currents associated with the start-up voltage ramp. the soft- start feature is disabled by setting the value of ton_rise to any value less than 0.25 ms. the ltc3883 pwm always uses discontinuous mode during the ton_ rise operation. in discontinuous mode, the bottom gate is turned off as soon as reverse current is detected in the inductor. this will allow the regulator to start up into a pre-biased load. when the ton_max_fault_limit is reached, the part transitions to continuous mode or burst, if so programmed. if ton_max_fault_limit is set to zero, there is no time limit and the part transitions to the desired conduction mode after ton_rise completes and v out has exceeded the vout_uv_fault_limit and iout_oc is not present. setting ton_max_fault_limit to a value of 0 is not recommended. this described method of start-up se- quencing is time based. s equencing the default mode for sequencing the output on and off is time based. the output is enabled after waiting ton _ delay amount of time following either the run pin going high, a
ltc3883/LTC3883-1 18 3883f o pera t ion pmbus command to turn on, or the v in pin voltage rising above a preprogrammed voltage. off sequencing is handled in a similar way. to assure proper sequencing, make sure all ics connect the share_ clk pins together and run pins together. if the run pins can not be connected together for some reason, set bit 2 of mfr_chan_config_ltc3883 to a 1. this bit requires the share_clk pin to be clocking before the power supply output can start. when the run pin is pulled low, the ltc3883 will hold the pin low for the mfr_ restart_ delay. the minimum mfr_ restart_ delay is toff_delay + toff_fall + 136 ms. this delay assures proper sequencing of all rails. the ltc3883 calculates this delay internally and will not process a shorter delay. however, a longer commanded mfr_restart_delay will be used by the part. the maximum allowed value is 65.52 seconds. v ol tage -b ased s equencing the gpio pin can be asserted when the uv threshold is exceeded. it is possible to feed the gpio pin from one ltc3883 into the run pin of the next ltc3883 in the sequence. to use the gpio pin for voltage based sequencing, set bit 12 of the mfr_gpio_propagate_ ltc3883 command = 1. bit 12 is the vout_uvuf which is the deglitched vout_ uv comparator. using the deglitched vout_uv fault limit is recommended because there is little appreciable time delay between the comparator crossing the uv threshold and the gpio pin releasing this can be implemented across multiple ltc3883s. the vout_uvuf has a 250 s minimum pulse width filter. if the gpio_fault_response command is not set to ignore, the part will latch off and never be able to start. if the v out voltage bounces around the uv threshold for a long period of time it is possible for the gpio output to toggle more than once. to minimize this problem, set the ton_rise time under 100 ms. if a fault in the string of rails is detected, only the faulted rail and downstream rails will fault off. the rails in the string of devices in front of the faulted rail will remain on unless commanded off. s hutdown the ltc3883 supports two shutdown modes. the first mode is closed- loop shutdown response, with user- defined turn-off delay ( toff_delay) and ramp down rate ( toff_fall). the controller will maintain the mode of operation for toff_fall. in discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by the output capacitance and load current. the other shutdown mode occurs in response to a fault condition or loss of share_clk ( if bit 2 of mfr_chan_ config_ltc3883 is set to a 1) or v in falling below the vin_off threshold or gpio pulled low externally ( if the mfr_gpio_response is set to inhibit). under these conditions the power stage is disabled in order to stop the transfer of energy to the load as quickly as possible. the shutdown state can be entered from the soft-start or active regulation states either through user intervention (deasserting run or the pmbus operation command) or in response to a detected fault or an external fault via the bidirectional gpio pin, or loss of share_clk ( if bit 2 of mfr_chan_config_ltc3883 is set to a 1) or v in falling below the vin_off threshold. in hiccup mode, the controller responds to a fault by shutting down and entering the inactive state for a programmable delay time ( mfr_ retry_ delay ). this delay minimizes the duty cycle associated with autonomous retries if the fault that caused the shutdown disappears once the output is disabled. the retry delay time is determined by the longer of the mfr_retry_ delay command or the time required for the regulated output to decay below 12.5% of the programmed value. if multiple outputs are controlled by the same gpio pin, the decay time of the faulted output determines the retry figure 2. event (voltage) based sequencing ltc3883 voltage based sequencing by cascading gpios into run pins gpio = v out_uvuf run start ltc3883 3883 f02 run gpio = v out_uvuf to next channel in the sequence
ltc3883/LTC3883-1 19 3883f o pera t ion delay. if the natural decay time of the output is too long, it is possible to remove the voltage requirement of the mfr_retry_delay command by asserting bit 0 of mfr_ chan_ config_ lt c 3883. alternatively, the control- ler can be configured so that it remains latched- off follow- ing a fault and clearing requires user intervention such as toggling run or commanding the part off then on. l ight l oad c urrent o peration the ltc3883 has three modes of operation including high efficiency burst mode operation, discontinuous conduction mode or forced continuous conduction mode. mode selection is done using the mfr_pwm_mode_ lt c 3883 command ( discontinuous conduction is always the start- up mode, forced continuous is the default running mode). in burst mode operation the peak current in the inductor is set to approximately one- third of the maximum sense voltage even though the voltage on the i th pin indicates a lower value. if the average inductor current is higher than the load current, the error amplifier, ea, will decrease the voltage on the i th pin. when the i th voltage drops below approximately 0.5 v, the internal burst mode operation as- serts and both external mosfets are turned off. in burst mode operation, the load current is supplied by the output capacitor. as the output voltage decreases, the ea output begins to rise. when the output voltage drops sufficiently, burst mode operation is deasserted, and the controller resumes normal operation by turning on the top external mosfet on the next pwm cycle. if a controller is enabled for burst mode operation, the inductor current is not allowed to reverse. the reverse current comparator, i rev , turns off the bottom gate external mosfet just before the inductor current reaches zero, preventing it from reversing and going negative. thus, the controller can operate in discontinuous operation. in forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined solely by the voltage on the i th pin. in this mode, the efficiency at light loads is lower than in burst mode operation. however, continuous mode exhibits lower output ripple and less interference with audio circuitry. forced continuous conduction mode may result in reverse inductor current, which can cause the input supply to boost. the vin_ov_ fault_limit can detect this and turn off the offending channel. however, this fault is based on an adc read and can take up to 120 ms to detect. if there is a concern about the input supply boosting, keep the part in discontinuous conduction or burst mode operation. if the part is set to burst mode operation, as the inductor average current increases, the controller will automati- cally modify the operation from burst mode operation, to discontinuous mode to continuous mode. s witching f requency and p hase the switching frequency of the ltc3883s controller can be established with internal clock references or with an external time-base. the ltc3883 can be configured for an external clock input through the programmed value in nvm, a pmbus command or setting the r bottom resistor of the freq_cfg pin to 0 and the r top to open. the pmbus command frequency_switch is set to external clock. the mfr_ pwm_ config_ lt c 3883 command determines the relative phasing. the rconfig input can set the relative phasing with respect to the falling edge of sync. the master should be selected to be out of phase with the slave. the run pin must be low before the frequency and mfr_ pwm_ config_ lt c 3883 com - mands can be written to the ltc3883 . the relative phas- ing of all devices in a polyphase rail should be optimally phased. the relative phasing of each rail is 360/ n where n is the number of phases in the rail. if the ltc3883 is configured as the oscillator output on sync, the switching frequency source can be selected with either external configuration resistors or through serial bus programming. the freq_cfg configuration resistor pin can be used to select the frequency_switch and mfr_pwm_config_ltc3883 values as outlined in table 14. otherwise, the frequency_switch and mfr_ pwm_ config_ ltc3883 pmbus commands can be used to select pwm switching frequency and the pwm channel phase relationship. the phase and frequency relationships are completely independent of each other providing the numerous application options for the user. if the ltc3883 is configured to drive the sync pin using the programmed frequency_ switch command value,
ltc3883/LTC3883-1 20 3883f o pera t ion the sync pin will pull low at the desired clock rate with 500ns low pulse. care must be taken in the application to assure the capacitance on sync is minimized to assure the pull-up resistor versus the capacitor load has a low enough time constant for the application. in addition, a phase-locked loop ( pll) is available to synchronize the internal oscillator to an external clock source that is connected to the sync pin. all phase relationships are between the falling edge of sync and the rising edge of the ltc3883 tg output. multiple ltc3883s can be synchronized in order to realize polyphase arrays. o utput v oltage s ensing the differential amplifier allows remote, differential sens- ing of the load voltage with v sensen pins. the telemetry adc is fully differential and makes measurements of the output voltage at the v sensen pins. o utput c urrent s ensing for dcr current sense applications, a resistor in series with a capacitor is placed across the inductor. in this configuration, the resistor is tied to the fet side of the inductor while the capacitor is tied to the load side of the inductor as shown in figure 3. if the rc values are cho- sen such that the rc time constant matches the inductor time constant ( l/dcr, where dcr is the inductor series resistance), the resultant voltage (v dcr ) appearing across the capacitor will equal the voltage across the inductor series resistance and thus represent the current flowing through the inductor. the rc calculations are based on the room temperature dcr of the inductor. the rc time constant should remain constant, as a function of temperature. this assures the transient response of the circuit is the same regardless of the temperature. the dcr of the inductor has a large temperature coefficient, approximately 3900 ppm/c. the temperature coefficient of the inductor must be written to the mfr_iout_cal_ gain_tc command. the external temperature is sensed near the inductor and is used to modify the internal current limit circuit to maintain an essentially constant current limit with temperature. in this application, the i sense + pin is connected to the fet side of the capacitor while the i sense C pin is placed on the load side of the capacitor. the current sensed from the input is then given by the expression v dcr /dcr. v dcr is digitized by the ltc3883s telemetry adc with an input range of 128 mv, a noise floor of 7v rms , and a peak-peak noise of approximately 46.5v . the ltc3883 computes the inductor current using the dcr value stored in the iout_cal_gain command and the temperature coefficient stored in command mfr_iout_cal_gain_tc. the resulting current value is returned by the read_iout command. a uto c alibra tion using a patent pending auto- calibration routine, the ltc3883 can measure the actual dc resistance for dcr current sense applications. the measured value is used in read_iout measurements and eliminates the need for the user to know the actual resistance of the inductor. reference the subsection titled inductor dcr calibration in the applications information section for further detail. a ccura te dcr t empera ture c ompensa tion the ltc3883 uses a patent pending algorithm to dy- namically model the temperature rise from the external temperature sensor to the inductor core. refer to the accurate dcr temperature compensation subsection in the applications information section for complete details. i nput c urrent s ensing to sense the total input current consumed by the ltc3883 and the power stage, a resistor is placed between the supply voltage and the drain of the top n- channel mosfet. the v in_sns and i in_sns pins are connected to the sense resistor through 100 filter resistors. both pins need to be decoupled to gnd. a filter capacitor needs to be connected across the v in_ sns and i in_ sns pins. refer to figure 25, low noise input current sense circuit for further details. the filtered voltage is amplified by the internal high side current sense amplifier and digitized by the ltc3883 s telemetry adc. the input current sense amplifier has three gain settings of 2x, 4 x, and 8 x set by the bits 5:4 of the mfr_ pwm_ mode command. the maximum input sense voltage for the three gain settings is 50mv, 20mv, and 8 mv respectively. the ltc3883 computes the input current using the r value stored in the iin _ cal _ gain
ltc3883/LTC3883-1 21 3883f figure 3. load sharing connections for 2-phase operation o pera t ion command. the resulting measured powerstage current is returned by the read_iin command. the mfr_ read_ iin_ chan command returns the calculated powerstage current based on the read_iout value multiplied by the read_duty_cycle value. the ltc3883 uses an internal 1 sense resistor to measure the v in pin supply current being consumed by the ltc3883. this value is returned by the mfr _ read _ ichip command. refer to the subsection titled input current sense amplifier in the applications information section for further detail. l oad s haring multiple ltc3883s can be arrayed in order to provide a balanced load-share solution by bussing the necessary pins. figure 3 illustrates the shared connections required for load sharing. the frequency must only be programmed on one of the ltc3883s. the other(s) must be programmed to external clock. e xternal /i nternal t empera ture s ense external temperature can be best measured using a remote diode-connected pnp transistor such as the mmbt3906. the emitter should be connected to the tsns pin while the base and collector terminals of the pnp transistor should be returned to the ltc3883s gnd pin, preferably using a star connection . it is possible to connect the collector of the pnp to the source of the bottom mosfet. this may optimize board layout allowing the pnp closer proximity to the power fets. the base of the pnp must still be tied to ground. for best noise immunity, the connections should be routed differentially and a 10nf capacitor should be placed in parallel with the diode connected pnp. two different currents are applied to the diode ( nominally 2 a and 32a ) and the 100 100 100 100 ltc3883 + power stage i th v in power stage i in_sns v in_sns ltc3883 + power stage i th note: some connectors and components omitted for clarity i sense + i sense ? v sense + v sense ? control v supply smbalert fault pwm clock share clock run alert gpio sync share_clk run alert gpio sync share_clk i sense + i sense ? pgnd gnd pgnd 3883 f03 gnd v sense + v sense ? load i in_sns v in_sns v in power stage
ltc3883/LTC3883-1 22 3883f o pera t ion temperature is calculated from the ? v be measurement. the external transistor temperature is digitized by the telemetry adc, and the value is returned by the pmbus read_ temperature_1 command. the read_ temperature_ 2 command returns the junction temperature of the ltc3883 using an on-chip diode. the slope of the external temperature sensor can be modified with the temperature slope coefficient stored in mfr_temp_1_gain. typical pnps require temperature slope adjustments slightly less than 1. the mmbt3906 has a recommended value in this command of approximately mfr_temp_1_gain = 0.991 based on the ideality factor of 1.01. simply invert the ideality factor to calculate the mfr_temp_1_gain. different manufacturers and differ- ent lots may have different ideality factors. consult with the manufacturer to set this value. the offset of the external temperature sense can be adjusted by mfr_temp_1_offset. a value of 0 in this command sets the temperature offset to C273.15c. if the pnp cannot be placed in direct contact with the inductor, the slope or offset can be increased to account for temperature mismatches. if the user is adjusting the slope, the intercept point is at absolute zero , C273.15 c, so small adjustments in slope can change the apparent measured temperature significantly. another way to artificially increase the slope of the temperature term is to increase the mfr_iout_cal_gain_tc term. this will modify the temperature slope with respect to room temperature. if an external temperature sense element is not used, the tsns pin must be shorted to gnd. the ut_fault_limit must be set to C275c , and the ut_ fault_ response must be set to ignore. the user also needs to set the iout_cal_gain_tc to a value of 0. rconfig (r esistor c onfigura tion ) p ins the pins freq_cfg, vout_cfg and vtrim_cfg can be used to select important operating parameters without programming the configuration eeprom. connecting these pins to external resistor dividers selects the switching frequency, output voltage and basic power management supervisor parameters. the asel pin is used to select the unique device bus address. connect this pin to an external resistor divider to select the device address. always use a resistor divider to select the device address. setting the device address in eeprom is allowed, but can create problems if the device address is somehow lost by the host. it is safe and prudent to use the asel pin to set the device address. if rconfig pins are floated, the value stored in the corresponding nvm command is used. if bit 6 of the mfr_config_all_ltc3883 configuration command is asserted in nvm, the resistor inputs are ignored upon power-up except for asel which is always respected. the resistor configuration pins are only measured during a power-up reset or after an mfr_reset command is executed. the v out_ cfg and v trim pin settings are described in tables 12 and 13. these pins select the output voltage for the ltc3883s analog pwm controller. if both pins are open, the vout_command command is loaded from nvm to determine the output voltage. the following parameters are set as a percentage of the output voltage if the rconfig pins are used to determined output voltage: n vout _ o v _ fault _ limit .................................... +1 0% n vout _ o v _ warn _ limit .................................. + 7. 5% n vout _ ma x ....................................................... +7. 5% n vout _ m argin _ high ......................................... + 5% n power _ go od _ on ............................................. C 7% n power _ go od _off ............................................ C 8% n vout _ m argin _ low .......................................... C 5% n vout _ u v _ warn _ limit .................................. C6.5% n vout _ u v _ fault _ limit ...................................... C 7% the freq_cfg pin settings are described in table 14. this pin selects the switching frequency and phase relationship between the pwm channel and sync pin. to synchronize to an external clock, the part must be put into external clock figure 4. temperature sense circuit tsns mmbt3906 ltc3883 10nf gnd gnd 3883 f04
ltc3883/LTC3883-1 23 3883f o pera t ion mode ( freq_cfg pin shorted to ground). if no external clock is supplied, the part will clock at the lowest free- running frequency of the internal pwm oscillator. this low clock rate will increase the ripple current of the inductor possibly producing undesirable operation. if the external sync signal is missing or misbehaving, a pll lock status fault will be indicated in the status_mfr_specific command. if the user does not wish to see the pll_fault even if there is not a valid synchronization signal at power up, bit 3 of the mfr_config_all_ lt c 3883 command must be asserted. if the sync pin is connected between multiple ics only one of the ics can be the oscillator, all other ics must be configured to external clock. the asel pin settings are described in table 15. this pin selects the bottom 4 bits of the slave address for the ltc3883. the three most significant bits are retrieved from the nvm mfr_address command. if the pin is floating, the 7- bit value stored in nvm mfr_address command is used to determine the slave address. for more detail, refer to table 15a. note: per the pmbus specification, pin programmed parameters can be overridden by commands from the digital interface with the exception of asel which is always honored. do not set any part address to 0 x5a or 0x5b because these are global addresses and all parts will respond to them. f ault d etection and h andling a variety of fault and warning reporting and handling mechanisms are available. fault and warning detection capabilities include: n input ov/fault protection and uv warning n average input oc warn n output ov/uv fault and warn protection n output oc fault and warn protection n internal and external overtemperature fault and warn protection n external undertemperature fault and warn protection n cml fault (communication, memory or logic) n external fault detection via the bidirectional gpio pins. in addition, the ltc3883 can map any combination of fault indicators to the gpio pin using the propagate gpio response commands, mfr _ gpio_ propagate_ ltc3883. typical usage of the gpio pin is as a driver for an external crowbar device, overtemperature alert, overvoltage alert or as an interrupt to cause a microcontroller to poll the fault commands. alternatively, the gpio pin can be used as an input to detect external faults downstream of the controller that require an immediate response. the gpio pin can also be configured as a power good output. power good indicates the controller output is above the power good threshold. at power-up the pin will initially be three- state. if it is necessary to have the desired polarity on the pin at power-up in this configuration, attach a schottky diode between the run pin of the propagated power good signal and the gpio pin. the cathode must be attached to run and the anode to the gpio pin. if the gpio pin is set to a power good status, the mfr_gpio_response must be ignore otherwise there is a latched off condition with the controller. as described in the soft- start section, it is possible to control start- up through concatenated events. if gpio is used to drive the run pin of another controller, the unfiltered vout_ uv fault limit should be mapped to the gpio pin. any fault or warning event will cause the alert pin to assert low. the pin will remain asserted low until the clear_ faults command is issued, the fault bit is written to a 1 or bias power is cycled or a mfr_reset command is issued, or the run pin is toggled off/on or the part is commanded off/on via pmbus or an ara command operation is performed. the mfr_gpio_propagate_ lt c 3883 command determines if the gpio pin is pulled low when a fault is detected; however, the alert pin is always pulled low if a fault or warning is detected and the status bits are updated. output and input fault event handling is controlled by the corresponding fault response byte as specified in tables 5 to 9. shutdown recovery from these types of faults can either be autonomous or latched. for autonomous recovery, the faults are not latched, so if the fault condition is not present after the retry interval has elapsed, a new soft- start is attempted. if the fault persists, the controller will continue to retry. the retry interval is specified by the
ltc3883/LTC3883-1 24 3883f o pera t ion mfr_retry_delay command and prevents damage to the regulator components by repetitive power cycling, assuming the fault condition itself is not immediately destructive. the mfr_retry_delay must be greater than 120ms. it can not exceed 83.88 seconds. the gpio pin of the ltc3883 can share faults with all ltc pmbus products including the ltc3880, ltc2974, ltc2978, ltc4676 module, etc. in the event of an internal fault, one or more of the ltc3883s is configured to pull the bussed gpio pins low. the other ltc3883s are then configured to shut down when the gpio pin bus is pulled low. for autonomous group retry, the faulted ltc3883 is configured to let go of the gpio pin bus after a retry interval, assuming the original fault has cleared. all the ltc3883s in the group then begin a soft-start sequence. if the fault response is latch_off, the gpio pin remains asserted low until either the run pin is toggled off/on or the part is commanded off/on or the ara command operation is performed. the toggling of the run either by the pin or off/on command will clear faults associated with the ltc3883. if it is desired to have all faults cleared when either run pin is toggled, set bit 0 of mfr_ config_all_ lt c 3883 to a 1. the status of all faults and warnings is summarized in the status_word and status_byte commands. additional fault detection and handling capabilities are: crc failure the integrity of the nvm memory is checked after a power- on reset. a crc failure will prevent the controller from leaving the inactive state. if a crc failure occurs, the cml bit is set in the status_ byte and status_ word commands, the appropriate bit is set in the status_mfr_specific command, and the alert pin will be pulled low. nvm repair can be attempted by writing the desired configuration to the controller and executing a store_user_all command followed by a clear_faults command. the ltc3883 manufacturing section of the nvm is mirrored. the nvm has the ability to perform limited repair if either one of the two sections of the manufacturing section of the nvm if the configuration becomes corrupted . if a discrepancy is detected, the nvm crc fault in the status_mfr_specific command is set. if this bit remains set after being cleared by issuing a clear_ faults or writing a 1 to this bit, an irrecoverable internal fault has occurred. the user is cautioned to disable both output power supply rails associated with this specific part. there are no provisions for field repairing unrecoverable nvm faults in the manufacturing section. s erial i nterface the ltc3883 serial interface is a pmbus compliant slave device and can operate at any frequency between 10khz and 400 khz. the address is configurable using either the nvm or an external resistor divider. in addition the ltc3883 always responds to the global broadcast address of 0x5a (7 bit) or 0x5b (7 bit). the serial interface supports the following protocols defined in the pmbus specifications: 1) send command, 2) write byte , 3) write word , 4) group , 5) read byte , 6) read word and 7) read block. all read operations will return a valid pec if the pmbus master requests it. if the pec_ required bit is set in the mfr_config_all_ lt c 3883 command, the pmbus write operations will not be acted upon until a valid pec has been received by the ltc3883. communication failure pec write errors ( if pec_required is active), attempts to access unsupported commands, or writing invalid data to supported commands will result in a cml fault. the cml bit is set in the status_byte and status_word commands, the appropriate bit is set in the status_cml command, and the alert pin is pulled low. d evice a ddressing the ltc3883 offers four different types of addressing over the pmbus interface, specifically : 1) global, 2) device, 3) rail addressing and 4) alert response address (ara). global addressing provides a means of the pmbus master to address all ltc3883 devices on the bus. the ltc3883 global address is fixed 0x5a (7 bit) or 0xb4 (8 bit) and can- not be disabled. device addressing provides the standard means of the pmbus master communicating with a single instance of an ltc3883. the value of the device address is set
ltc3883/LTC3883-1 25 3883f opera t ion by a combination of the asel configuration pin and the mfr_address command. device addressing can be disabled by writing a value of 0 x80 to the mfr_address. rail addressing provides a means of the pmbus master addressing a set of ltc3883 s connected to the same output rail, simultaneously. this is similar to global addressing, however, the pmbus address can be dynamically assigned by using the mfr_ rail_ address command. it is recom- mended that rail addressing should be limited to command write operations. all four means of pmbus addressing require the user to employ disciplined planning to avoid addressing conflicts. r esponses to v out and i out f aults v out ov and uv conditions are monitored by comparators . the ov and uv limits are set in three ways. n as a percentage of the v out if using the resistor con- figuration pins n in nvm if either programmed at the factory or through the gui n by pmbus command the i in and i out overcurrent monitors are performed by adc readings and calculations. thus these values are based on average currents and can have a time latency of up to 120 ms. the i out calculation accounts for the sense resistor and the temperature coefficient of the resistor. the input channel current is equal to the sum of output current times the pwm duty cycle plus the input offset current for each channel. if this calculated input current exceed the in_oc_warn_limit the alert pin is pulled low and the iin_oc_warn bit is asserted in the status_input command. the digital processor within the ltc3883 provides the ability to ignore the fault, shut down and latch off or shut down and retry indefinitely ( hiccup). the retry interval is set in mfr_retry_delay and can be from 120ms to 83.88 seconds in 1 ms increments. the shutdown for ov/uv and oc can be done immediately or after a user selectable deglitch time. output overvoltage fault response a programmable overvoltage comparator ( ov) guards against transient overshoots as well as long-term over- voltages at the output. in such cases, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared regardless of the pmbus vout_ ov_fault_ response command byte value. this hardware level fault response delay is typically 2 s from the overvoltage condition to bg asserted high. using the vout_ ov_fault_response command, the user can select any of the following behaviors: n ov pull-down only (ov cannot be ignored) n shut down (stop switching) immediatelylatch off n shut down immediatelyretry indefinitely at the time interval specified in mfr_retry_dela y either the latch off or retry fault responses can be de- glitched in increments of (0-7) ? 10 s. see table 5. output undervoltage response the response to an undervoltage comparator output can be either: n ignore n shut down immediatelylatch off n shut down immediatelyretry indefinitely at the time interval specified in mfr_retry_dela y the uv responses can be deglitched. see table 6. peak output overcurrent fault response due to the current mode control algorithm, peak output current across the inductor is always limited on a cycle by cycle basis. the value of the peak current limit is specified in sense voltage in the ec table. the current limit circuit operates by limiting the i th maximum voltage. if dcr sens- ing is used, the i th maximum voltage has a temperature dependency directly proportional to the tc of the dcr of the inductor. the ltc3883 automatically monitors the external temperature sensors and modifies the maximum allowed i th to compensate for this term.
ltc3883/LTC3883-1 26 3883f opera t ion the overcurrent fault processing circuitry can execute the following behaviors: n current limit indefinitely n shut down immediatelylatch off n shut down immediatelyretry indefinitely at the time interval specified in mfr_retry_dela y the overcurrent responses can be deglitched in increments of (0-7) ? 16 ms. see table 7 r esponses to t iming f aults ton_max_fault_limit is the time allowed for v out to rise and settle at start-up. the ton_max_fault_limit condition is predicated upon detection of the vout_uv_ fault_limit as the output is undergoing a soft_start sequence. the ton_max_fault_limit time is started after ton_delay has been reached and a soft_start sequence is started. the resolution of the ton_max_ fault_limit is 10 s. if the vout_uv_fault_limit is not reached within the ton_max_fault_limit time, the response of this fault is determined by the value of the ton_max_fault_response command value. this response may be one of the following: n ignore n shut down (stop switching) immediatelylatch off n shut down immediatelyretry indefinitely at the time interval specified in mfr_retry_dela y this fault response is not deglitched. a value of 0 in ton_ max_fault_limit means the fault is ignored. the ton_max_fault_limit should be set longer than the ton_rise time. it is recommended ton_max_fault_ limit always be set to a non-zero value, otherwise the output may never come up and no flag will be set to the user. see table 9. r esponses to v in ov f aults v in overvoltage is measured with the muxd adc; there- fore, the response is naturally deglitched by the 120ms typical response time of the adc. the fault responses are: n ignore n shut down immediatelylatch off n shut down immediatelyretry indefinitely at the time interval specified in mfr_retry_dela y see table 9. r esponses to ot/ut f aults overtemperature fault responseinternal an internal temperature sensor protects against nvm damage. above 85c , no writes to nvm are recommended. above 130 c, the part disables the nvm and does not re- enable until the internal temperature has dropped to 125 c. the ltc3883 sets bit 7 of the status_temperature command ( ot warn) above 130 c, and this bit cannot be cleared until the internal temperature has dropped to 125c. above 160 c, the ltc3883 disables the pwm and does not re-enable the pwm until the internal temperature has dropped to 150 c. the part sets bit 6 of the status_ temperature command ( ot fault) above 160 c, and this bit cannot be cleared until the internal temperature has dropped to 150 c. temperature is measured by the adc. internal temperature faults cannot be ignored. internal temperature limits cannot be adjusted by the user. see table 9. overtemperature and undertemperature fault responseexternals an external temperature sensors can be used to sense critical circuit elements like the inductor and power mosfets. the ot_fault_response and ut_fault_ respose commands are used to determine the appropri- ate response to an overtemperature and undertemperature condition, respectively. if no external sense element is used (not recommended) set the ut_fault_response to ignore and set the ut_fault_limit to C275c. the fault responses are: n ignore n shut down immediatelylatch off n shut down immediatelyretry indefinitely at the time interval specified in mfr_retry_dela y see table 9.
ltc3883/LTC3883-1 27 3883f opera t ion r esponses t o i nput o vercurrent a nd o utput u ndercurrent f aults input overcurrent and output undercurrent are measured with the muxd adc. both of these measurements are naturally deglitched by the 120 ms typical response time of the adc. the fault responses are: n ignore n shut down immediatelylatch off n shut down immediatelyretry indefinitely at the time interval specified in mfr_retry_dela y see table 9. r esponses to e xternal f aults when the gpio pin is pulled low, the other bit is set in the status_word command, the appropriate bit is set in the status_mfr_specifc command, and the alert pin is pulled low. responses are not deglitched. the ltc3883 can be configured to ignore or shut down then retry in response to its gpio pin going low by modifying the mfr_ gpio_ response command. to avoid the alert pin asserting low when gpio is pulled low, assert bit 1 of mfr_chan_config_ lt c 3883. f ault l ogging the ltc3883 has fault logging capability. data is logged into memory in the order shown in table 11. the data is stored in a continuously updated buffer in ram. when a fault event occurs, the fault log buffer is copied from the ram buffer into nvm . fault logging is allowed at temperatures above 85c ; however, retention of 10 years is not guaranteed. when the die temperature exceeds 130c, the fault logging is delayed until the die temperature drops below 120c . the fault log data remains in nvm until a mfr_ fault_ log_ clear command is issued. issuing this command re - enables the fault log feature. before re - enabling fault log, be sure no faults are present and a clear_faults command has been issued. when the ltc3883 powers-up, it checks the nvm for a valid fault log. if a valid fault log exists in nvm, the valid fault log bit in the status_mfr_specific command will be set and an alert event will be generated. also, fault logging will be blocked until the ltc3883 has received a mfr_fault_log_clear command before fault logging will be re-enabled. the information is stored in eeprom in the event of any fault that disables the controller. the gpio pin being externally pulled low will not trigger a fault logging event. b us t imeout f ailure the ltc3883 implements a timeout feature to avoid hang- ing the serial interface. the data packet timer begins at the first start event before the device address write byte. data packet information must be completed within 20ms or the ltc3883 will three-state the bus and ignore the given data packet. data packet information includes the device address byte write, command byte, repeat start event (if a read operation), device address byte read ( if a read operation), all data bytes and the pec byte if applicable. the ltc3883 allows longer pmbus timeouts for block read data packets. this timeout is proportional to the length of the block read. the additional block read timeout applies primarily to the mfr_fault_log command. in no circumstances will the timeout period be less than the t timeout_smb specification of 32ms (typical). the user is encouraged to use as high a clock rate as possible to maintain efficient data packet transfer between all devices sharing the serial bus interface. the ltc3883 supports the full pmbus frequency range from 10 khz to 400khz. s imilarit y b et ween pmb us , smb us and i 2 c 2-w ire i nterf ace the pmbus 2- wire interface is an incremental extension of the smbus. smbus is built upon i 2 c with some minor differences in timing, dc parameters and protocol. the pmbus/smbus protocols are more robust than simple i 2 c byte commands because pmbus/ smbus provide time-outs to prevent bus hangs and optional packet er- ror checking ( pec) to ensure data integrity. in general, a master device that can be configured for i 2 c communica- tion can be used for pmbus communication with little or no change to hardware or firmware. repeat start (restart) is not supported by all i 2 c controllers but is required for
ltc3883/LTC3883-1 28 3883f opera t ion smbus/pmbus reads. if a general purpose i 2 c controller is used, check that repeat start is supported. the ltc3883 supports the maximum smbus clock speed of 100 khz and is compatible with the higher speed pmbus specification (between 100 khz and 400 khz) if clock stretching is enabled. for robust communication and operation refer to the note section in the pmbus command summary. clock stretching is enabled by assserting bit 1 of mfr_config_all_ lt c 3883. for a description of the minor extensions and exceptions pmbus makes to smbus, refer to pmbus specification part 1 revision 1.1: paragraph 5: transport. for a description of the differences between smbus and i 2 c, refer to system management bus ( smbus) speci- fication version 2.0: appendix bdifferences between smbus and i 2 c. pmb us s erial d igit al i nterf ace the ltc3883 communicates with a host ( master) using the standard pmbus serial bus interface. the timing diagram, figure 5, shows the timing relationship of the signals on the bus. the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources are required on these lines. the ltc3883 is a slave device. the master can com- municate with the ltc3883 using the following formats: n master transmitter, slave receiver n master receiver, slave transmitter figure 5. timing diagram figure 6. pmbus packet protocol diagram element key sda scl t hd(sta) t hd(dat) t su(sta) t su(sto) t su(dat) t low t hd(sda) t sp t buf start condition stop condition repeated start condition start condition t r t f t r t f t high 3883 f05 slave address data byte wr a a p 3883 f06 s 7 s start condition sr repeated start condition rd read (bit value of 1) wr write (bit value of 0) x shown under a field indicates that that field is required to have the value of x a acknowledge (this bit position may be 0 for an ack or 1 for a nack) p stop condition pec packet error code master to slave slave to master continuation of protocol 8 1 1 1 x x 1 1 ... the following pmbus protocols are supported: n write byte, write word, send byte n read byte, read word, block read n alert response address figures 7-16 illustrate the aforementioned pmbus proto- cols. all transactions support pec ( parity error check) and gcp ( group command protocol). the block read supports 255 bytes of returned data. for this reason, the pmbus timeout may be extended when reading the fault log. figure 6 is a key to the protocol diagrams in this section. pec is optional. a value shown below a field in the following figures is a mandatory value for that field.
ltc3883/LTC3883-1 29 3883f figure 7. write byte protocol figure 8. write word protocol figure 9. write byte protocol with pec figure 10. write word protocol with pec opera t ion table 1. data format terminology pmbus terminology meaning terminology for: specs, gui, application notes abbreviations for summary command table for more detail refer to the d ata format section of table 2 linear linear linear_5s_11s l11 page 35 linear (for voltage related commands) linear linear_16u l16 page 35 direct direct-manufacturer customized directmfr cf page 35 hex hex i16 ascii ascii asc register fields reg reg slave address command code data byte wr a a a p 3883 f07 s 7 8 8 1 1 1 1 1 1 slave address command code data byte low wr a a a p 3883 f08 s 7 8 8 1 data byte high 8 1 1 1 1 1 1 a slave address command code data byte wr a a a p 3883 f09 s 7 8 8 1 pec 8 1 1 1 1 1 1 a slave address command code data byte low wr a a a p 3883 f10 s 7 8 8 1 data byte high 8 pec 8 1 1 1 1 1 1 1 a a the data formats implemented by pmbus are: n master transmitter transmits to slave receiver. the transfer direction in this case is not changed. n master reads slave immediately after the first byte. at the moment of the first acknowledgment ( provided by the slave receiver) the master transmitter becomes a master receiver and the slave receiver becomes a slave transmitter. n combined format. during a change of direction within a transfer, the master repeats both a start condition and the slave address but with the r/ w bit reversed. in this case, the master receiver terminates the transfer by generating a nack on the last byte of the transfer and a stop condition. examples of these formats are shown in figures 7-16.
ltc3883/LTC3883-1 30 3883f opera t ion figure 11. send byte protocol figure 12. send byte protocol with pec figure 13. read word protocol figure 14. read word protocol with pec figure 16. read byte protocol with pec figure 15. read byte protocol slave address wr a a p 3883 f11 s 7 8 1 1 1 1 1 command code slave address command code pec wr a a a p 3883 f12 s 7 8 8 1 1 1 1 1 1 slave address command code slave address wr a a a p 3883 f13 s 7 8 7 1 data byte low 8 data byte high 8 1 1 1 1 s 1 1 1 1 1 a 1 rd a slave address command code slave address wr a a a pa 3883 f14 s 7 8 7 1 data byte low 8 data byte high pec 8 8 1 1 1 1 1 1 11 1 s 1 a 1 rd a slave address command code slave address wr a a s p 3883 f15 s 7 8 8 11 data byte 8 1 1 1 1 1 1 1 1 a rd a slave address command code slave address wr a a s p 3883 f16 s 7 8 8 11 data byte 8 1 1 1 1 1 1 1 1 a rd a 1 a pec refer to figure 6 for a legend. handshaking features are included to ensure robust system communication. please refer to the pmbus com- munication and command processing subsection of the applications information section for further details.
ltc3883/LTC3883-1 31 3883f pmb us c ommands the following tables list supported pmbus commands and manufacturer specific commands. a complete description of these commands can be found in the pmbus power system mgt protocol specification C part ii C revision 1.1. users are encouraged to reference this specification. exceptions or manufacturer specific implementations are listed below in table 2. floating point values listed in the default value column are either linear 16-bit signed ( pmbus section 8.3.1) or linear_5s_11s (pmbus section 7.1) format, whichever is appropriate for the com- mand. all commands from 0 xd0 through 0 xff not listed in this table are implicitly reserved by the manufacturer. users should avoid blind writes within this range of com- mands to avoid undesired operation of the part. all com- mands from 0 x00 through 0 xcf not listed in this table are implicitly not supported by the manufacturer. attempting to access non-supported or reserved commands may result in a cml command fault event. all output voltage settings and measurements are based on the vout_mode setting of 0x14. this translates to an exponent of 2 C12 . if pmbus commands are received faster than they are be- ing processed, the part may become too busy to handle new commands. in these circumstances the part follows the protocols defined in the pmbus specification v1.1, part?ii, section 10.8.7, to communicate that it is busy. the part includes handshaking features to eliminate busy errors and simplify error handling software while ensur- ing robust communication and system behavior. please refer to the subsection titled pmbus communication and command processing in the applications information section for further details. command name cmd code description type d ata format units nvm default value page page 0x00 provides integration with multi-page pmbus devices. r/w byte reg 0x00 64 operation 0x01 operating mode control. on/off, margin high and margin low. r/w byte reg y 0x80 67 on_off_config 0x02 run pin and pmbus bus on/off command configuration. r/w byte reg y 0x1e 66 clear_faults 0x03 clear any fault bits that have been set. send byte na 93 write_protect 0x10 level of protection provided by the device against accidental changes. r/w byte reg y 0x00 64 store_user_all 0x15 store user operating memory to eeprom. send byte na 101 restore_user_all 0x16 restore user operating memory from eeprom. send byte na 101 capability 0x19 summary of pmbus optional communication protocols supported by this device. r byte reg 0xb0 91 vout_mode 0x20 output voltage format and exponent (2 C12 ). r byte reg 2 C12 0x14 71 vout_command 0x21 nominal output voltage set point. r/w word l16 v y 1.0 0x1000 73 vout_max 0x24 upper limit on the output voltage the unit can command regardless of any other commands. r/w word l16 v y 5.5 0x5800 72 vout_margin_high 0x25 margin high output voltage set point. must be greater than vout_command. r/w word l16 v y 1.05 0x10cd 72 vout_margin_low 0x26 margin low output voltage set point. must be less than vout_command. r/w word l16 v y 0.95 0x0f33 73 vout_transition_rate 0x27 rate the output changes when vout commanded to a new value. r/w word l11 v/ms y 0.25 aa00 80 frequency_switch 0x33 switching frequency of the controller. r/w word l11 khz y 350 0xfabc 70 table 2. summary ( note: the data format abbreviations are detailed at the end of this table.) pmb us c omman d s ummary
ltc3883/LTC3883-1 32 3883f command name cmd code description type d ata format units nvm default value page vin_on 0x35 input voltage at which the unit should start power conversion. r/w word l11 v y 6.5 0xcb40 71 vin_off 0x36 input voltage at which the unit should stop power conversion. r/w word l11 v y 6.0 0xcb00 71 iout_cal_gain 0x38 the ratio of the voltage at the current sense pins to the sensed current. for devices using a fixed current sense resistor, it is the resistance value in m. r/w word l11 m y 1.8 0xbb9a 74 vout_ov_fault_limit 0x40 output overvoltage fault limit. r/w word l16 v y 1.1 0x119a 72 vout_ov_fault_ response 0x41 action to be taken by the device when an output overvoltage fault is detected. r/w byte reg y 0xb8 83 vout_ov_warn_limit 0x42 output overvoltage warning limit. r/w word l16 v y 1.075 0x1133 72 vout_uv_warn_limit 0x43 output undervoltage warning limit. r/w word l16 v y 0.925 0x0ecd 73 vout_uv_fault_limit 0x44 output undervoltage fault limit. r/w word l16 v y 0.9 0x0e66 73 vout_uv_fault_ response 0x45 action to be taken by the device when an output undervoltage fault is detected. r/w byte reg y 0xb8 84 iout_oc_fault_limit 0x46 output overcurrent fault limit. r/w word l11 a y 29.75 0xdbb8 76 iout_oc_fault_ response 0x47 action to be taken by the device when an output overcurrent fault is detected. r/w byte reg y 0x00 86 iout_oc_warn_limit 0x4a output overcurrent warning limit. r/w word l11 a y 20.0 0xda80 77 ot_fault_limit 0x4f external overtemperature fault limit. r/w word l11 c y 100.0 0xeb20 79 ot_fault_response 0x50 action to be taken by the device when an external overtemperature fault is detected, r/w byte reg y 0xb8 87 ot_warn_limit 0x51 external overtemperature warning limit. r/w word l11 c y 85.0 0xeaa8 79 ut_fault_limit 0x53 external undertemperature fault limit. r/w word l11 c y C40.0 0xe580 79 ut_fault_response 0x54 action to be taken by the device when an external undertemperature fault is detected. r/w byte reg y 0xb8 88 vin_ov_fault_limit 0x55 input supply overvoltage fault limit. r/w word l11 v y 15.5 0xd3e0 70 vin_ov_fault_ response 0x56 action to be taken by the device when an input overvoltage fault is detected. r/w byte reg y 0x80 82 vin_uv_warn_limit 0x58 input supply undervoltage warning limit. r/w word l11 v y 6.3 0xcb26 70 iin_oc_warn_limit 0x5d input supply overcurrent warning limit. r/w word l11 a y 10.0 0xd280 78 power_good_on 0x5e output voltage at or above which a power good should be asserted. r/w word l16 v y 0.93 0x0ee1 73 power_good_off 0x5f output voltage at or below which a power good should be de-asserted. r/w word l16 v y 0.92 0x0eb8 73 ton_delay 0x60 time from run and/or operation on to output rail turn-on. r/w word l11 ms y 0.0 0x8000 80 pmb us c omman d s ummary
ltc3883/LTC3883-1 33 3883f pmb us c omman d s ummary command name cmd code description type d ata format units nvm default value page ton_rise 0x61 time from when the output starts to rise until the output voltage reaches the vout commanded value. r/w word l11 ms y 8.0 0xd200 80 ton_max_fault_limit 0x62 maximum time from v out_en on for vout to cross the vout_uv_fault_limit. r/w word l11 ms y 10.00 0xd280 80 ton_max_fault_ response 0x63 action to be taken by the device when a ton_ max_fault event is detected. r/w byte reg y 0xb8 85 toff_delay 0x64 time from run and/or operation off to the start of toff_fall ramp. r/w word l11 ms y 0.0 0x8000 81 toff_fall 0x65 time from when the output starts to fall until the output reaches zero volts. r/w word l11 ms y 8.00 0xd200 81 toff_max_warn_limit 0x66 maximum allowed time, after toff_fall completed, for the unit to decay below 12.5%. r/w word l11 ms y 150 0xf258 81 status_byte 0x78 one byte summary of the units fault condition. r/w byte reg na 93 status_word 0x79 tw o byte summary of the units fault condition. r/w word reg na 93 status_vout 0x7a output voltage fault and warning status. r/w byte reg na 94 status_iout 0x7b output current fault and warning status. r/w byte reg na 94 status_input 0x7c input supply fault and warning status. r/w byte reg na 94 status_temperature 0x7d external temperature fault and warning status for read_temerature_1. r/w byte reg na 94 status_cml 0x7e communication and memory fault and warning status. r/w byte reg na 95 status_mfr_specific 0x80 manufacturer specific fault and state information. r/w byte reg na 95 read_vin 0x88 measured input supply voltage. r word l11 v na 98 read_iin 0x89 measured input supply current. r word l11 a na 98 read_vout 0x8b measured output voltage. r word l16 v na 98 read_iout 0x8c measured output current. r word l11 a na 99 read_temperature_1 0x8d external diode junction temperature. this is the value used for all temperature related processing, including iout_cal_gain. r word l11 c na 99 read_temperature_2 0x8e internal junction temperature. does not affect any other commands. r word l11 c na 99 read_duty_cycle 0x94 duty cycle of the top gate control signal. r word l11 % na 99 read_pout 0x96 calculated output power. r word l11 w na 99 read_pin 0x97 calculated input power r word l11 w na 99 pmbus_revision 0x98 pmbus revision supported by this device. current revision is 1.1. r byte reg fs 0x11 91 mfr_id 0x99 the manufacturer id of the ltc3883 in ascii. r string asc lt c 91 mfr_model 0x9a manufacturer part number in ascii. r string asc ltc3883 92 mfr_revision 0x9b manufacturer part revision in ascii. r string asc fs na 92 mfr_location 0x9c location of the final test of the ltc3883 in ascii. r string asc fs na 91 mfr_date 0x9d date of the final test of the ic yymmdd in ascii. r string asc fs na 91 mfr_vout_max 0xa5 maximum allowed output voltage. r word l16 v 5.5 0x5800 74 user_data_00 0xb0 oem reserved. typically used for part serialization. r/w word reg y na 90
ltc3883/LTC3883-1 34 3883f command name cmd code description type d ata format units nvm default value page user_data_01 0xb1 manufacturer reserved for ltpowerplay. r/w word reg y na 90 user_data_02 0xb2 oem reserved. typically used for part serialization r/w word reg y na 90 user_data_03 0xb3 an nvm word available for the user. r/w word reg y 0x0000 90 user_data_04 0xb4 an nvm word available for the user. r/w word reg y 0x0000 90 mfr_t_self_heat 0xb8 reports the calculated self heat value attributed to the inductor. r word l11 c na 75 mfr_iout_cal_gain_ tau_inv 0xb9 coefficient used to emulate thermal time constant. r/w word l11 s C1 y 0.0 0x8000 75 mfr_iout_cal_gain_ theta 0xba used to calculate the instance inductor self heating effect. r/w word l11 c/watt y 0.0 0x8000 75 mfr_ee_unlock 0xbd unlock user eeprom for access by mfr_ee_ erase and mfr_ee_ data commands. r/w byte reg na 105 mfr_ee_erase 0xbe initialize user eeprom for bulk programming by mfr_ee_ data . r/w byte reg na 106 mfr_ee_ data 0xbf data transferred to and from eeprom using sequential pmbus word reads or writes. supports bulk programming. r/w word reg na 106 mfr_chan_config_ lt c 3883 0xd0 configuration bits that are channel specific. r/w byte reg y 0x1f 65 mfr_config_all_ lt c 3883 0xd1 general configuration bit. r/w byte reg y 0x09 66 mfr_gpio_propagate_ lt c 3883 0xd2 configuration that determines which faults are propagated to the gpio pin. r/w word reg y 0x2993 89 mfr_pwm_mode_ lt c 3883 0xd4 configuration for the pwm engine. r/w byte reg y 0xd2 68 mfr_gpio_response 0xd5 action to be taken by the device when the gpio pin is externally asserted low. r/w byte reg y 0xc0 90 mfr_ot_fault_ response 0xd6 action to be taken by the device when an internal overtemperature fault is detected. r byte reg 0xc0 87 mfr_iout_peak 0xd7 report the maximum measured value of read_ iout since last mfr_clear_peaks. r word l11 a na 99 mfr_retry_delay 0xdb retry interval during fault retry mode. r/w word l11 ms y 350 0xfabc 82 mfr_restart_delay 0xdc minimum time the run pin is held low by the ltc3883. r/w word l11 ms y 500 0xfbe8 82 mfr_vout_peak 0xdd maximum measured value of read_vout since last mfr_clear_peaks. r word l16 v na 99 mfr_vin_peak 0xde maximum measured value of read_vin since last mfr_clear_peaks. r word l11 v na 100 mfr_temperature_1_ peak 0xdf maximum measured value of external temperature (read_temperature_1) since last mfr_clear_peaks. r word l11 c na 100 mfr_read_iin_peak 0xe1 maximum measured value of read_iin command since last mfr_clear_peaks r word l11 a na 100 mfr_clear_peaks 0xe3 clears all peak values. send byte na 93 mfr_read_ichip 0xe4 measured supply current of the ltc3883 r word l11 a na 100 pmb us c omman d s ummary
ltc3883/LTC3883-1 35 3883f pmb us c omman d s ummary note 1: commands indicated with y indicate that these commands are stored and restored using the store_user_all and restore_user_ all commands, respectively. note 2: commands with a default value of na indicate not applicable. commands with a default value of fs indicate factory set on a per part basis. note 3: the ltc3883 contains additional commands not listed in this table. reading these commands is harmless to the operation of the ic; however, the contents and meaning of these commands can change without notice. note 4: some of the unpublished commands are read-only and will generate a cml bit 6 fault if written. note 5: writing to commands not published in this table is not permitted. note 6: the user should not assume compatibility of commands between different parts based upon command names. always refer to the manufacturers data sheet for each part for a complete definition of a commands function. lt c has made every reasonable attempt to keep command functionality compatible between parts; however, differences may occur to address product requirements. command name cmd code description type d ata format units nvm default value page mfr_pads 0xe5 digital status of the i/o pads. r word reg na 96 mfr_address 0xe6 sets the 7-bit i 2 c address byte. r/w byte reg y 0x4f 65 mfr_special_id 0xe7 manufacturer code representing the ltc3883 and revision r word reg 0x43xx 92 mfr_iin_cal_gain 0xe8 the resistance value of the input current sense element in m. r/w word l11 m y 5 0xca80 77 mfr_fault_log_store 0xea command a transfer of the fault log from ram to eeprom. this causes the part to behave as if a channel has faulted off. send byte na 102 mfr_trim 0xeb contact the factory. this command is used for diagnostics. r block cf na 92 mfr_fault_log_clear 0xec initialize the eeprom block reserved for fault logging and clear any previous fault logging locks. send byte na 105 mfr_read_iin_chan 0xed calculated input current based upon read_iout and duty_cycle. r word l11 a na 100 mfr_fault_log 0xee fault log data bytes. this sequentially retrieved data is used to assemble a complete fault log. r block reg y na 102 mfr_common 0xef manufacturer status bits that are common across multiple lt c chips. r byte reg na 96 mfr_compare_user_ all 0xf0 compares current command contents with nvm. send byte na 101 mfr_temperature_2_ peak 0xf4 peak internal die temperature since last mfr_ clear_peaks. r word l11 c na 100 mfr_pwm_config_ lt c 3883 0xf5 set numerous parameters for the dc/dc controller including phasing. r/w byte reg y 0x10 69 mfr_ iout_ cal_ gain_ tc 0xf6 temperature coefficient of the current sensing element. r/w word cf y 3900 0x0f3c 74 mfr_rvin 0xf7 the resistance value of the v in pin filter element in m. r/w word l11 m y 3000 0x12ee 71 mfr_temp_1_gain 0xf8 sets the slope of the external temperature sensor. r/w word cf y 1.0 0x4000 78 mfr_temp_1_offset 0xf9 sets the offset of the external temperature sensor with respect to C273.1c r/w word l11 c y 0.0 0x8000 78 mfr_rail_address 0 xfa common address for polyphase outputs to adjust common parameters. r/w byte reg y 0x80 65 mfr_rom_crc 0xfc factory use only. r word i16 na 92 mfr_reset 0xfd commanded reset without requiring a power down. send byte na 68
ltc3883/LTC3883-1 36 3883f *d ata f orma t l11 linear_5s_11s pmbus data field b[15:0] value = y ? 2 n where n = b[15:11] is a 5-bit twos complement integer and y = b[10:0] is an 11-bit twos complement integer example: for b[15:0] = 0x9807 = b10011_000_0000_0111 value = 7 ? 2 C13 = 854 ? 10 C6 from pmbus spec part ii: paragraph 7.1 l16 linear_16u pmbus data field b[15:0] value = y ? 2 n where y = b[15:0] is an unsigned integer and n = vout_mode_parameter is a 5-bit twos complement exponent that is hardwired to C12 decimal example: for b[15:0] = 0x9807 = b1001_1000_0000_0000 value = 19456 ? 2 C12 = 4.75 from pmbus spec part ii: paragraph 8.2 reg register pmbus data field b[15:0] or b[7:0]. bit field meaning is defined in detailed pmbus command description. i16 integer word pmbus data field b[15:0] value = y where y = b[15:0] is a 16 bit unsigned integer example: for b[15:0] = 0x9807 = b1001_1000_0000_0111 value = 38919 (decimal) cf custom format value is defined in detailed pmbus command description. this is often an unsigned or twos complement integer scaled by an mfr specific constant. asc ascii format a variable length string of text characters conforming to iso/iec 8859-1 standard. pmb us c omman d s ummary
ltc3883/LTC3883-1 37 3883f a pplica t ions i n f orma t ion the typical application on the back page is a basic ltc3883 application circuit. the ltc3883 can be configured to use either dcr ( inductor resistance) sensing or low value resistor sensing. the choice between the two current sensing schemes is largely a design trade-off between cost, power consumption and accuracy. dcr sensing is becoming popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. the ltc3883 can nominally account for the temperature dependency of the dcr sensing element. the accuracy of the current reading and current limit are typically limited by the accuracy of the dcr resistor ( accounted for in the iout_cal_gain parameter of the ltc3883). thus current sensing resistors provide the most accurate current sense and limiting for the application. other external component selection is driven by the load requirement, and begins with the selection of r sense ( if r sense is used) and inductor value. next, the power mosfets are selected. then the input and output capacitors are selected. finally the current limit is selected. all of these components and ranges are required to be determined prior to calculating the external compensation components. the current limit range is required because the two ranges (25 mv to 50 mv vs 37.5 mv to 75 mv) have different ea gains set with bit 7 of the mfr_pwm_mode_ ltc3883 command. the voltage range bit also modifies the loop gain and impacts the compensation network set with bits 5, 6 of mfr_pwm_config_ lt c 3883. all other programmable parameters do not affect the loop gain, allowing parameters to be modified without impact to the transient response to load. c urrent l imit p rogramming the ltc3883 has two ranges of current limit programming and a total of eight levels within each range. refer to the iout_ oc_ fault_ limit section of the pmbus commands. within each range the error amp gain is fixed, resulting in constant loop gain. the ltc3883 will account for the dcr of the inductor and automatically update the current limit as the inductor temperature changes. the temperature coefficient of the dcr is stored in the mfr_ iout_ tc command. for the best current limit accuracy, use the 75 mv setting. the 25 mv setting will allow for the use of very low dcr inductors or sense resistors, but at the expense of cur- rent limit accuracy. keep in mind this operation is on a cycle-by-cycle basis and is only a function of the peak inductor current. the average inductor current is monitored by the adc converter and can provide a warning if too much average output current is detected. the overcurrent fault is detected when the ith voltage hits the maximum value. the digital processor within the ltc3883 provides the ability to either ignore the fault, shut down and latch off or shut down and retry indefinitely ( hiccup). refer to the overcurrent portion of the operation section for more detail . i sense + and i sense C p ins the i sense + and i sense C pins are the inputs to the current comparator and the a/d. the common mode input voltage range of the current comparators is 0 v to 5.5 v. both the sense pins are high impedance inputs with small base currents typically less than 1 a. when the i sense pin volt- ages are between 0 v and 1.4v , the small base currents flow out of the sense pins. when the i sense pin voltages are greater than 1.4 v, the base currents flow into the i sense pins. the high impedance inputs to the current compara- tors allow accurate dcr sensing. do not float these pins during normal operation. filter components mutual to the i sense lines should be placed close to the ic. the positive and negative traces should be routed differentially and kelvin connected to the current sense element, see figure 17. a non-kelvin connection elsewhere can add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. in a polyphase system, poor placement of the sensing element will result in sub- optimal current sharing between power stages. if dcr sensing is used (figure 18 a), sense resistor r1 should be placed close to the switching node to prevent noise from figure 17. optimal sense line placement c out to sense filter, next to the controller inductor or r sense 3883 f17
ltc3883/LTC3883-1 38 3883f v in v in intv cc boost tg sw bg pgnd filter components placed near sense pins i sense + i sense ? sgnd ltc3883 v out 3883 f018b c f ? 2 rf esl/r s pole-zero cancellation sense resistor plus parasitic inductance r s esl c f r f r f v in v in intv cc boost tg sw bg pgnd *place c1 near sense + , sense ? pins inductor dcr r3 optional c2 >1f l i sense + i sense ? sgnd ltc3883 v out 3883 f18a r1 r2c1* ((r1+ r3)||r2) c1 = r3 = r1 l 2 dcr iout_cal_gain = dcr r2 r1 + r2 + r3 a pplica t ions i n f orma t ion the current comparator has a maximum threshold v sense(max) determined by the i limit setting. the input common mode range of the current comparator is 0 v to 5.5v ( if v in is greater than 6 v). the current comparator threshold sets the peak of the inductor current, yielding a maximum average output current i max equal to the peak value less half the peak-to-peak ripple current )i l . to calculate the sense resistor value, use the equation: r sense = v sense(max) i max + ? i l 2 due to possible pcb noise in the current sensing loop, the ac current sensing ripple of )v sense = )i l ? r sense also needs to be checked in the design to get a good signal-to- noise ratio. in general, for a reasonably good pcb layout, a 15 mv minimum )v sense voltage is recommended as a conservative number to start with, either for r sense or dcr sensing applications. for previous generation current mode controllers, the maximum sense voltage was high enough ( e.g ., 75mv for the ltc1628/ ltc3728 family) that the voltage drop across the parasitic inductance of the sense resistor represented a relatively small error. in the new highest current density solutions; however, the value of the sense resistor can be less than 1 m and the peak sense voltage can be less than 20mv. in addition, inductor ripple currents greater than 50% with operation up to 1 mhz are becoming more common. under these conditions, the voltage drop across the sense resistor s parasitic inductance is no longer negligible. a typical sensing circuit using a discrete resistor is shown in figure 18b . in previous generations of controllers, a small rc filter placed near the ic was commonly used to reduce the effects of the capacitive and inductive noise coupled in the sense traces on the pcb. a typical filter consists of two series 100 resistors connected to a parallel 1000pf capacitor, resulting in a time constant of 200ns. this same rc filter with minor modifications, can be used to extract the resistive component of the current sense signal in the presence of parasitic inductance. for example, figure 19 illustrates the voltage waveform across a 2 m resistor with a 2010 footprint. the waveform is the superposition of a purely resistive component and a figure 18a. inductor dcr current sense circuit figure 18b. resistor current sense circuit coupling into sensitive small-signal nodes. the capacitor c1 should be placed close to the ic pins. this impedance difference can result in loss of accuracy in the current reading of the adc. the current reading accuracy can be improved by matching the impedance of the two pins. to accomplish this add a series resistor between v out and i sense C equal to r1. a capacitor of 1 f or greater should be placed in parallel with this resistor. if the peak voltage is <75mv at room temperature, r2 is not required. l ow v alue r esistor c urrent s ensing a typical sensing circuit using a discrete resistor is shown in figure 18 b. r sense is chosen based on the required output current.
ltc3883/LTC3883-1 39 3883f a pplica t ions i n f orma t ion purely inductive component. it was measured using two scope probes and waveform math to obtain a differential measurement. based on additional measurements of the inductor ripple current and the on-time, t on , and off-time, t off , of the top switch, the value of the parasitic inductance was determined to be 0.5nh using the equation: esl = v esl(step) ? i l ? t on ? t off t on + t off (1) if the rc time constant is chosen to be close to the para- sitic inductance divided by the sense resistor ( l/r), the resultant waveform looks resistive, as shown in figure 20. for applications using low maximum sense voltages, check the sense resistor manufacturers data sheet for information about parasitic inductance. in the absence of data, measure the voltage drop directly across the sense resistor to extract the magnitude of the esl step and use equation 1 to determine the esl. however, do not overfilter the signal. keep the rc time constant less than or equal to the inductor time constant to maintain a sufficient ripple voltage on v rsense for optimal operation of the current loop controller. i nductor dcr c urrent s ensing for applications requiring the highest possible efficiency at high load currents, the ltc3883 is capable of sensing the voltage drop across the inductor dcr, as shown in figure 18 a. the dcr of the inductor represents the small amount of dc winding resistance of the copper, which can be less than 1 m for todays low value, high current inductors. in a high current application requiring such an inductor, conduction loss through a sense resistor would cost a few points of efficiency compared to dcr sensing. if the external (r1 + r3)||r 2 ? c1 time constant is chosen to be exactly equal to the l/dcr time constant, the voltage drop across the external capacitor,c1, is equal to the drop across the inductor dcr multiplied by r2/(r1+r2). r2 scales the voltage across the sense terminals for applications where the dcr is greater than the target sense resistor value. the dcr value is entered as the iout_ cal_ gain in m unless r 2 is required. if r 2 is used: iout _cal _gain = dcr ? r2 r1 + r2 + r3 if there is no need to attenuate the signal, r2 can be removed. to properly dimension the external filter components, the dcr of the inductor must be known. it can be measured using an accurate rlc meter, but the dcr tolerance is not always the same and varies with temperature. consult the manufacturers data sheets for detailed information. the ltc3883 will account for temperature variation if the correct parameter is entered into the mfr_iout_cal_gain_tc command. typically the resistance has a 3900ppm/c coefficient. using the inductor ripple current value from the inductor value calculation section, the target sense resistor value is: r sense(equiv) = v sense(max) i max + ? i l 2 to ensure that the application will deliver full load current over the full operating temperature range, be sure to pick the optimum i limit value accounting for errors in the dcr versus the mfr_iout_cal_gain parameter entered. figure 19. voltage measured directly across r sense figure 20. voltage measured after the r sense filter 500ns/div v sense 20mv/div 3883 f19 v esl(step) 500ns/div v sense 20mv/div 3883 f20
ltc3883/LTC3883-1 40 3883f a pplica t ions i n f orma t ion next, determine the dcr of the inductor. where provided, use the manufacturers maximum value, usually given at 20 c. increase this value to account for errors in the temperature sensing element of 3 c to 5 c and any additional errors associated with the proximity of the temperature sensor element to the inductor. c1 is usually selected to be in the range of 0.047 f to 4.7f. this forces (r1 + r3)||r2 to be approximately 2k. adding optional elements r3 and c2 shown in figure 18a will minimize offset errors associated with the isns leak- age currents. set r3 equal to the value of r1. set c2 to a value of 1 f or greater to ensure adequate noise filtering. the equivalent resistance (r1 + r3)||r2 is scaled to the room temperature inductance and maximum dcr: r1 + r3 ( ) ||r2 = l 2 ? dcr at 20 c ( ) ? c1 the maximum power loss in r1 is related to the duty cycle, and will occur in continuous mode at the maximum input voltage: p loss r1 = v in(max) ? v out ( ) ? v out r1 ensure that r1 has a power rating higher than this value. if high efficiency is necessary at light loads, consider this power loss when deciding whether to use dcr sensing or sense resistors. light load power loss can be modestly higher with a dcr network than with a sense resistor due to the extra switching losses incurred through r1. however, dcr sensing eliminates a sense resistor, reduc- ing conduction losses and provides higher efficiency at heavy loads. peak efficiency is about the same with either method. selecting burst mode operation or discontinuous mode will improve the converter efficiency at light loads regardless of the current sensing method. to maintain a good signal-to-noise ratio for the current sense signal, use a minimum ?v sense of 10 mv to 15mv. for a dcr sensing application, the actual ripple voltage will be determined by the equation: ? v sense = v in ? v out r1 ? c1 ? v out v in ? f osc s lope c ompensation and i nductor p eak c urrent slope compensation provides stability in constant frequency current mode architectures by preventing sub-harmonic oscillations at high duty cycles. this is accomplished internally by adding a compensation ramp to the inductor current signal at duty cycles in excess of 35%. the ltc3883 uses a patented current limit technique that counteracts the compensating ramp. this allows the maximum inductor peak current to remain unaffected throughout all duty cycles. i nductor v alue c alcula tion given the desired input and output voltages, the inductor value and operating frequency, f osc , directly determine the inductor peak-to-peak ripple current: i ripple = v out v in ? v out ( ) v in ? f osc ? l lower ripple current reduces core losses in the inductor, esr losses in the output capacitors, and output voltage ripple. thus, highest efficiency operation is obtained at the lowest frequency with a small ripple current. achieving this, however, requires a large inductor. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . note that the largest ripple current occurs at the highest input voltage. to guarantee that the ripple current does not exceed a specified maxi- mum, the inductor should be chosen according to: l v out v in ? v out ( ) v in ? f osc ? i ripple
ltc3883/LTC3883-1 41 3883f a pplica t ions i n f orma t ion i nductor c ore s election once the inductor value is determined, the type of induc- tor must be selected. core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance. as the inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses increase. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con- centrate on copper loss and preventing saturation. ferrite core materials saturate hard, which means that the induc- tance collapse abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! p ower mosfet and s chot tky d iode (o p tional ) s election two external power mosfets must be selected for each controller in the ltc3883: one n-channel mosfet for the top ( main) switch, and one n-channel mosfet for the bottom (synchronous) switch. the peak-to-peak drive levels are set by the intv cc volt- age. this voltage is typically 5 v. consequently, logic-level threshold mosfets must be used in most applications. the only exception is if low input voltage is expected (v in < 5 v); then, sub-logic level threshold mosfets (v gs(th) < 3 v) should be used. pay close attention to the bv dss specification for the mosfets as well; most of the logic- level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on- resistance, r ds(on) , miller capacitance, c miller , input voltage and maximum output current. miller capacitance, c miller , can be approximated from the gate charge curve usually provided on the mosfet manufacturers data sheet. c miller is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in v ds . this result is then multiplied by the ratio of the application applied v ds to the gate charge curve specified v ds . when the ic is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle = v out v in synchronous switch duty cycle = v in ? v out v in the mosfet power dissipations at maximum output current are given by: p main = v out v in i max ( ) 2 1 + ( ) r ds(on) + v in ( ) 2 i max 2 ? ? ? ? ? ? r dr ( ) c miller ( ) ? 1 v intvcc ? v th(min) + 1 v th(min) ? ? ? ? ? ? ? ? ? f osc p sync = v in ? v out v in i max ( ) 2 1 + ( ) r ds(on) where d is the temperature dependency of r ds(on) and r dr (approximately 2?) is the effective driver resistance at the mosfets miller threshold voltage. v th(min) is the typical mosfet minimum threshold voltage. both mosfets have i 2 r losses while the topside n- channel equation includes an additional term for transition losses, which are highest at high input voltages. for v in < 20v the high current efficiency generally improves with larger mosfets, while for v in > 20 v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. the term (1 + d ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but d = 0.005/ c can be used as an approximation for low voltage mosfets.
ltc3883/LTC3883-1 42 3883f a pplica t ions i n f orma t ion the optional schottky diodes conduct during the dead time between the conduction of the two power mosfets. these prevent the body diodes of the bottom mosfets from turn- ing on, storing charge during the dead time and requiring a reverse recovery period that could cost as much as 3% in efficiency at high v in . a 1 a to 3 a schottky is generally a good compromise for both regions of operation due to the relatively small average current. larger diodes result in additional transition losses due to their larger junction capacitance. v ariable d ela y t ime , s of t -s t art and o utput v ol tage r amping the ltc3883 must enter the run state prior to soft-start. the run pin is released after the part initializes and v in is greater than the vin_on threshold. if multiple ltc3883s are used in an application, they should be configured to share the same run pins. they all hold their respective run pins low until all devices initialize and v in exceeds the vin_on threshold for all devices. the share_clk pin assures all the devices connected to the signal use the same time base. after the run pin releases, the controller waits for the user- specified turn - on delay ( ton_ delay) prior to initiating an output voltage ramp. multiple ltc3883s and other ltc parts can be configured to start with variable delay times. to work correctly, all devices use the same timing clock ( share_clk) and all devices must share the run pin. this allows the relative delay of all parts to be synchronized. the actual variation in the delay will be dependent on the highest clock rate of the devices connected to the share_clk pin ( all linear technology ics are configured to allow the fastest share_clk signal to control the timing of all devices). the share_ clk signal can be 10% in frequency, thus the actual time delays will have proportional variance. soft-start is performed by actively regulating the load voltage while digitally ramping the target voltage from 0.0v to the commanded voltage set point. the rise time of the voltage ramp can be programmed using the ton_rise command to minimize inrush currents associated with the start-up voltage ramp. the soft-start feature is disabled by setting ton_rise to any value less than 0.250ms. the ltc3883 will perform the necessary math internally to assure the voltage ramp is controlled to the desired slope. however, the voltage slope can not be any faster than the fundamental limits of the power stage. the shorter ton_ rise time is set, the more jagged the ton_ rise ramp will appear. the number of steps in the ramp is equal to ton_rise/0.1ms. the ltc3883 pwm will always use discontinuous mode during the ton_rise operation. in discontinuous mode, the bottom gate is turned off as soon as reverse current is detected in the inductor. this will allow the regulator to start up into a pre-biased load. there is no tracking feature in the ltc3883; however, two outputs can be given the same ton_ rise and ton_delay times to effectively ramp up at the same time. if the run pin is released at the same time and both ltc3883s use the same time base, the outputs will track very closely. if the circuit is in a polyphase configuration, all timing parameters must be the same. the described method of start- up sequencing is time based. for concatenated events it is possible to control the run pin based on the gpio pin of a different controller. the gpio pin can be configured to release when the output voltage of the converter is greater than the vout_ uv_ fault_ limit. it is recommended to use the deglitched v out uv fault limit because there is little appreciable time delay between the converter crossing the uv threshold and the gpio pin releasing. the deglitched output can be enabled by setting the mfr_ gpio_ propagate_ vout_ uvuf bit in the mfr_ gpio_ propagate_ ltc3883 command . (refer to the mfr section of the pmbus commands in this document). the deglitched signal may have some glitching as the v out signal transitions through the comparator threshold. a small internal digital filter of 250 s has been added to minimize this problem. to minimize the risk of gpio pins glitching, make the ton_rise times less than 100ms. if unwanted transitions still occur on gpio , place a capacitor to ground on the gpio pin to filter the waveform. the rc time-constant of the filter should be set sufficiently fast to assure no appreciable delay is incurred. a value of 300 s to 500 s will provide some additional filtering without significantly delaying the trigger event.
ltc3883/LTC3883-1 43 3883f a pplica t ions i n f orma t ion d igital s ervo m ode for maximum accuracy in the regulated output voltage, enable the digital servo loop by asserting bit 6 of the mfr_pwm_mode_ltc3883 command. in digital servo mode, the ltc3883 will adjust the regulated output voltage based on the adc voltage reading. every 90 ms the digital servo loop will step the lsb of the dac ( nominally 1.375mv or 0.6875 mv depending on the voltage range bit) until the output is at the correct adc reading. at power- up this mode engages after ton_max_fault_limit unless the limit is set to 0 ( infinite). if the ton_max_fault_limit is set to 0 ( infinite), the servo begins after ton_rise is complete and vout has exceeded the vout_uv_fault_limit. this same point in time is when the output changes from discontinuous to the programmed mode as indicated in mfr_pwm_mode_ lt c 3883 bits 0 and 1. refer to figure?21 for details on the vout waveform under time based sequencing. if the ton_max_fault_limit is set to a value greater than 0 and the ton_max_fault_response is not set to ignore 0x00, the servo begins: 1. after the ton_rise sequence is complete; 2. after the ton_max_fault_limit time has expired and both vout_uv_fault and iout_oc_fault are not present. the maximum rise time is limited to 1.3 seconds. in a polyphase configuration it is recommended only one of the control loops have the digital servo mode enabled. this will assure the various loops do not work against each other due to slight differences in the reference circuits. s of t o ff (s equenced o ff ) in addition to a controlled start- up, the ltc3883 also supports controlled turn- off. the toff_ delay and toff_ fall functions are shown in figure 22. toff_ fall is processed when the run pin goes low or if the part is commanded off. if the part faults off or gpio is pulled low externally and the part is programmed to respond to this, the output will three- state rather than exhibiting a controlled ramp. the output will decay as a function of the load. the output voltage will operate as shown in figure 22 so long as the part is in forced continuous mode and the toff_fall time is sufficiently slow that the power stage can achieve the desired slope. the toff_fall time can only be met if the power stage and controller can sink figure 21. timing controlled v out rise figure 22. toff_delay and toff_fall dac voltage error (not to scale) time delay of many seconds digital servo mode enabled final output voltage reached ton_max_fault_limit ton_rise time 3883 f21 ton_delay v out toff_fall toff_delay time 3883 f22 v out if the ton_max_fault_limit is set to a value greater than 0 and the ton_max_fault_response is set to ignore 0x00, the servo begins: 1. after the ton_rise sequence is complete 2. after the ton_ max_ fault_ limit time is reached; and 3. after the vout_uv_fault_limit has been exceed or the iout_oc_fault_limit is not longer active.
ltc3883/LTC3883-1 44 3883f a pplica t ions i n f orma t ion sufficient current to assure the output is a zero volts by the end of the fall time interval. if the toff_fall time is set shorter than the time required to discharge the load capacitance, the output will not reach the desired zero volt state. at the end of toff_fall, the controller will cease to sink current and v out will decay at the natural rate determined by the load impedance. if the controller is in discontinuous mode, the controller will not pull negative current and the output will be pulled low by the load, not the power stage. the maximum fall time is limited to 1.3 seconds. the shorter toff_fall time is set, the more jagged the toff_fall ramp will appear. the number of steps in the ramp is equal to toff_fall/0.1ms. intv cc r egulator the ltc3883 features an npn linear regulator that sup- plies power to intv cc from the v in supply. intv cc powers the gate drivers, v dd33 and much of the ltc3883 internal circuitry. the linear regulator produces 5 v at the intv cc pin when v in is greater than 6.5 v. the regulator can sup- ply a peak current of 100 ma and must be bypassed to ground with a minimum of 1 f ceramic capacitor or low esr electrolytic capacitor. no matter what type of bulk capacitor is used, an additional 0.1 f ceramic capacitor placed directly adjacent to the intv cc and pgnd pins is highly recommended. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers. the npn linear regulator on the LTC3883-1 is not present and an external 5v supply is needed. h igh input voltage application in which large mosfets are being driven at high frequencies may cause the maxi- mum junction temperature rating for the ltc3883 to be exceeded. the intv cc current, of which a large percent- age is due to the gate charge current, may be supplied by either the internal 5 v linear regulator or from an external 5v regulator on the LTC3883-1. if the ltc3883 is used with the internal regulator activated, the power through the ic is equal to v in ? i intvcc . the gate charge current is dependent on operating frequency as discussed in the ef- ficiency considerations section. the junction temperature can be estimated by using the equations in note 2 of the electrical characteristics. for example, at 70 c ambient, the ltc3883 intv cc current is limited to less than 52ma from a 24v supply: t j = 70c + 52ma ? 24v ? 44c/w = 125c to prevent the maximum junction temperature from being exceeded, a LTC3883-1 can be used. in the LTC3883-1, the intv cc linear regulator is disabled and approximately 2ma of current is supplied internally from v in . significant system efficiency and thermal gains can be realized by powering the extv cc pin from a switching 5 v regulator. the v in current resulting from the gate driver and control circuitry will be scaled by a factor of: v extvcc v in ? ? ? ? ? ? 1 efficiency ? ? ? ? ? ? tying the extv cc pin to a 5 v supply ( LTC3883-1 only) reduces the junction temperature in the previous example from 125c to: t j = 70c + 52ma ? 5 v ? 44c/w + 2ma ? 24 v ? 44c/w = 103c do not tie intv cc on the ltc3883 to an external supply because intv cc will attempt to pull the external supply high and hit current limit, significantly increasing the die temperature. for applications where v in is 5 v, tie the v in and intv cc pins together and tie the combined pins to the 5 v input with a 1 or 2.2 resistor as shown in figure 23. to mini- mize the voltage drop caused by the gate charge current a low esr capacitor must be connected to the v in /intv cc (extv cc ) pins. this configuration will override the intv cc ( extv cc ) linear regulator and will prevent intv cc ( extv cc ) from dropping too low. make sure the intv cc (extv cc ) figure 23. setup for a 5v input r vin 1 c in 3883 f23 5v c intvcc 4.7f + intv cc /extv cc ltc3883 LTC3883-1 v in
ltc3883/LTC3883-1 45 3883f a pplica t ions i n f orma t ion voltage exceeds the r ds(on) test voltage for the mosfets which is typically 4.5 v for logic level devices. the uvlo on intv cc (extv cc ) is set to approximately 4 v. both the ltc3883 and LTC3883-1 are valid for this configuration. t opside mosfet d river s uppl y (c b , d b ) external bootstrap capacitors c b connected to the boost pin supplies the gate drive voltages for the topside mos- fets. capacitor c b in the block diagram is charged though external diode d b from intv cc when the sw pin is low. when one of the topside mosfets is to be turned on, the driver places the c b voltage across the gate source of the desired mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v intvcc . the value of the boost capacitor c b needs to be 100 times that of the total input capacitance of the topside mosfet(s). the reverse breakdown of the external schottky diode must be greater than v in(max) . when adjusting the gate drive level , the final arbiter is the total input current for the regulator. if a change is made and the input current decreases, then the efficiency has improved. if there is no change in input current, then there is no change in efficiency. pwm jitter has been observed in some designs operating at higher v in /v out ratios. this jitter does not substantially affect the circuit accuracy. referring to figure 24, pwm jitter can be removed by inserting a series resistor with a value of 1 to 5 between the cathode of the diode and the boost pin. a resistor case size of 0603 or larger is recommended to reduce esl and achieve the best results. u nder voltage l ockout the ltc3883 is initialized by an internal threshold-based uvlo where v in must be approximately 4 v and intv cc / extv cc , v dd33 , v dd25 must be within approximately 20% of the regulated values. in addition, v dd33 must be within approximately 7% of the targeted value before the run pin is released. after the part has initialized, an additional comparator monitors v in . the vin_on threshold must be exceeded before the power sequencing can begin. when v in drops below the vin_off threshold, the run pin will be pulled low and v in must increase above the vin_on threshold before the controller will restart. the normal start-up sequence will be allowed after the vin_on threshold is crossed. it is possible to program the contents of the nvm in the application if the v dd33 supply is externally driven. this will activate the digital portion of the ltc3883 without engaging the high voltage sections. pmbus communications are valid in this supply configuration. if v in has not been applied to the ltc3883, bit 3 ( nvm not initialized)in mfr_common will be asserted low. if this condition is detected, the part will only respond to addresses 5 a and 5 b. to initialize the part issue the following set of commands: global address 0 x5b command 0 xbd data 0 x2b followed by global address 5 b command 0 xbd and data 0 xc4. the part will now respond to the correct address. configure the part as desired then issue a store_user_all. when v in is applied a mfr_reset command must be issued to allow the pwm to be enabled and valid adc conversions to be read. c in and c out s election in conti nuous mode, the source current of the top mo sfet is a square wave of duty cycle (v out )/(v in ). to prevent large voltage transients, a low esr capacitor sized for the maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c in required i rms i max v in v out ( ) v in ? v out ( ) ? ? ? ? 1/2 this formula has a maximum at v in = 2 v out , where i rms = i out /2. this simple worst-case condition is com- monly used for design because even significant deviations figure 24. boost circuit to minimize pwm jitter v in tgate ltc3883/ LTC3883-1 sw d b intv cc /extv cc boost c b 0.2f 1 to 5 v in c intvcc 10f 3883 f24 bgate pgnd
ltc3883/LTC3883-1 46 3883f a pplica t ions i n f orma t ion do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capaci- tor, or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. due to the high operating frequency of the ltc3883, ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question. the benefit of using two ltc3883 2- phase operation can be calculated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. the total rms power lost is lower when both controllers are operating due to the reduced overlap of current pulses required through the input capacitors esr. this is why the input capacitors requirement cal- culated above for the worst-case controller is adequate for the dual controller design. also, the input protection fuse resistance, battery resistance, and pc board trace resistance losses are also reduced due to the reduced peak currents in a 2- phase system. the overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. the sources of the top mosfets should be placed within 1 cm of each other and share a common c in (s). separating the sources and c in may pro- duce undesirable voltage and current resonances at v in . a small (0.1 f to 1 f) bypass capacitor between the chip v in pin and ground, placed close to the ltc3883, is also suggested. a 2.2? C 10? resistor placed between c in (c1) and the v in pin provides further isolation between the two ltc3883s. the selection of c out is driven by the effective series resistance ( esr). typically, once the esr requirement is satisfied, the capacitance is adequate for filtering. the output ripple (?v out ) is approximated by: ? v out i ripple esr + 1 8fc out ? ? ? ? ? ? where f is the operating frequency, c out is the output capacitance and i ripple is the ripple current in the inductor. the output ripple is highest at maximum input voltage since i ripple increases with input voltage. f ault c onditions the ltc3883 gpio pin is configurable to indicate a variety of faults including ov, uv, oc, ot, timing faults, peak overcurrent faults. in addition the gpio pin can be pulled low by external sources indicating a fault in some other portion of the system. the fault response is configurable and allows the following options: n ignore n shut down immediatelylatch off n shut down immediatelyretry indefinitely at the time interval specified in mfr_retry_dela y refer to the pmbus section of the data sheet and the pmbus specification for more details. the ov response is automatic. if an ov condition is de- tected, tg goes low and bg is asserted. fault logging is available on the ltc3883. the fault log- ging is configurable to automatically store data when a fault occurs that causes the unit to fault off. the header portion of the fault logging table contains peak values. it is possible to read these values at any time . this data will be useful while troubleshooting the fault. if the ltc3883 internal temperature is in excess of 85c, the write into the nvm is not recommended. the data will still be held in ram, unless the 3.3 v supply uvlo thresh- old is reached. if the die temperature exceeds 130 c all nvm communication is disabled until the die temperature drops below 120c.
ltc3883/LTC3883-1 47 3883f a pplica t ions i n f orma t ion o pen -d rain p ins the ltc3883 has the following open-drain pins: 3.3 v pins 1. gpio 2. sync 3. share_clk 4. pgood 5v pins (5 v pins operate correctly when pulled to 3.3v.) 1. run 2. aler t 3. scl 4. sda all the above pins have on-chip pull-down transistors that can sink 3 ma at 0.4 v. the low threshold on the pins is 1.4 v; thus, plenty of margin on the digital signals with 3ma of current. for 3.3 v pins, 3 ma of current is a 1.1k resistor. unless there are transient speed issues associ- ated with the rc time constant of the resistor pull-up and parasitic capacitance to ground, a 10 k resistor or larger is generally recommended. for high speed signals such as the sda, scl and sync, a lower value resistor may be required. the rc time con- stant should be set to 1/3 to 1/5 the required rise time to avoid timing issues. for a 100 pf load and a 400khz pmbus communication rate, the rise time must be less than 300 ns. the resistor pull-up on the sda and scl pins with the time constant set to 1/3 the rise time: r pullup = t rise 3 ? 100pf = 1k the closest 1% resistor value is 1 k. be careful to minimize parasitic capacitance on the sda and scl pins to avoid communication problems. to estimate the loading capaci- tance, monitor the signal in question and measure how long it takes for the desired signal to reach approximately 63% of the output value. this is one time constant. the sync pin has an on-chip pull-down transistor with the output held low for nominally 500 ns. if the internal oscillator is set for 500 khz and the load is 100 pf and a 3x time constant is required, the resistor calculation is as follows: r pullup = 2s ? 500ns 3 ? 100pf = 5k the closest 1% resistor is 4.99k. if timing errors are occurring or if the sync frequency is not as fast as desired, monitor the waveform and determine if the rc time constant is too long for the application. if possible reduce the parasitic capacitance. if not reduce the pull up resistor sufficiently to assure proper timing. p hase -l ocked l oop and f requency s ynchroni z a tion the ltc3883 has a phase-locked loop ( pll) comprised of an internal voltage-controlled oscillator ( vco) and a phase detector. the pll is locked to the falling edge of the sync pin. the phase relationship between the pwm controller and the falling edge of sync is controlled by the lower 3? bits of the mfr_pwm_config_ lt c 3883 com- mand. for polyphase applications, it is recommended all the phases be spaced evenly. thus for a 2- phase system the signals should be 180 out of phase and a 4-phase system should be spaced 90. the phase detector is an edge-sensitive digital type that provides a known phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. the output of the phase detector is a pair of complemen - tar y current sources that charge or discharge the internal filter network. the pll lock range is guaranteed between 250khz and 1 mhz. nominal parts will have a range beyond this; however, operation to a wider frequency range is not guaranteed. the pll has a lock detection circuit. if the pll should lose lock during operation, bit 4 of the status _ mfr _ specific command is asserted and the alert pin is pulled low. the fault can be cleared by writing a 1 to the bit. if the user does not wish to see the pll_fault, even if a synchronization clock is not available at power up, bit 3 of the mfr_config_all_ lt c 3883 command must be asserted.
ltc3883/LTC3883-1 48 3883f a pplica t ions i n f orma t ion if the sync signal is not clocking in the application, the pll will run at the lowest free running frequency of the vco. this will be well below the intended pwm frequency of the application and may cause undesirable operation of the converter. if the pwm signal appears to be running at too high a frequency, monitor the sync pin. extra transitions on the falling edge will result in the pll trying to lock on to noise versus the intended signal. review routing of digital control signals and minimize crosstalk to the sync signal to avoid this problem. multiple ltc3883s are required to share the sync pin in polyphase configurations, for other configurations it is optional. if the sync pin is shared be- tween ltc3883s, only one ltc3883 can be programmed with a frequency output. all the other ltc3883s must be programmed to external clock. m inimum o n -t ime c onsidera tions minimum on-time, t on(min) , is the smallest time duration that the ltc3883 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn off the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t on(min) < v out v in ? f osc if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for the ltc3883 is approximately 90ns, with reasonably good pcb layout, minimum 30% inductor current ripple and at least 10mv C 15 mv ripple on the current sense signal. the minimum on-time can be affected by pcb switching noise in the voltage and cur- rent loop. as the peak current sense voltage decreases, the minimum on-time gradually increases to 130 ns. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with cor- respondingly larger current and voltage ripple. i nput c urrent s ense a mplifier the ltc3883 input current sense amplifier can sense the supply current into the v in pin using an internal sense resistor as well as the power stage current using an external sense resistor. high frequency noise caused by the discontinuous input current can cause input current measurement errors. the noise will be the greatest in high current applications and at large step-down ratios. care must be taken to mitigate the noise seen at the input current sense amplifier inputs and supply. this can be accomplished by careful layout as well as filtering at the v in , v in_sns and i insns pins. the v in pin should be filtered with a resistor and a ceramic capacitor located as close to the v in pin as possible. the supply side of the v in pin filter should be kelvin connected to the supply side of the r iinsns resistor. a 3 resistor should be sufficient for most applications. the resistor will cause an ir voltage drop from the supply to the v in pin due to the current flowing into the v in pin. to compensate for this voltage drop, the mfr_rvin command value should be set to the nominal resistor value. the ltc3883 will multiply the mfr_read_ichip measurement value by the user defined mfr_rvin value and add this voltage to the measured voltage at the v in pin. therefore read_vin = v vin_pin + (mfr_read_ichip ? mfr_rvin), so that this command will return the value of the voltage at the supply side of the v in pin filter. if no v in filter element is used, set mfr_rvin = 0. 10f r iinsns 100 m1 m2 1f 10f 10nf 10nf tg bg sw i in_sns v in_sns v in ltc3883 v in 3 3883 f25 100 figure 25. low noise input current sense circuit
ltc3883/LTC3883-1 49 3883f a pplica t ions i n f orma t ion both the v in_sns and i in_sns pins need to be filtered with a 1% tolerance 100? resistor to r iinsns and a 10nf ceramic capacitor to gnd. a larger value capacitor to gnd may be used for additional filtering. because the input current sense amplifier gain is calibrated for 100? filter resistors, any other filter resistance value will cause an input current measurement error. the amplifier input filter networks should be located as close to the v in_sns and i in_sns pins as possible. the capacitor from the intermediate bus to ground should be a low esr ceramic capacitor. it should be placed as close as possible to the drain of the top gate mosfet to supply high frequency transient input current. this will help prevent noise from the top gate mosfet current from feeding into the input current sense amplifier inputs and supply. if the input current sense amplifier is not used, short the v in , v in_sns , and i in_sns pins together. rconfig (e xternal r esistor c onfigura tion p ins ) the ltc3883 default nvm is programmed to respect the rconfig pins. if a user wishes the output voltage, pwm frequency and phasing to be set without programming the part or purchasing specially programmed parts, the freq_ cfg, vout _ cfg, and vtrim_ cfg pins can be used to establish these parameters. to save external components, the user may float the freq_ cfg, vout _ cfg, and vtrim_ cfg pins which will cause the ltc3883 to default to the respective parameters stored in nvm. the asel pin should always be programmed with a resistor divider to safeguard against a lost device address by the host. to externally program the rconfig pins connect a resistor divider between the v dd25 and gnd of the ltc3883. the rconfig pins are only monitored at initial power up and during a reset so modifying their values perhaps using an a/d after the part is powered will have no effect . 1% resis- tors or better must be used to assure proper operation. noisy clock signals should not be routed near these pins. voltage selection when an output voltage is set using the rconfig pins on vout_cfg and vtrim_cfg, the following parameters are set as a percentage of the output voltage: ? vout_ov_fault_limit +10% ? vout_ov_warn_limit +7.5% ? vout_max +7.5% ? vout_margin_high +5% ? power_good_on C7% ? power_good_off C8% ? vout_ margin_low C5% ? vout_uv_warn_limit C6.5% ? vout_uv_fault_limit C7% refer to tables 12 and 13 to set the output voltage using rconfig pins vout_cfg and vtrim_cfg. rtop is connected between vdd25 and the pin and rbottom is connected between the pin and sgnd . 1% resistors must be used to assure proper operation. the output voltage set point is equal to: v setpoint = vout_cfg + vtrim_cfg for example, if the vout_cfg pin has r top equal to 24.9 k and r bottom equal to 4.32 k, and vtrim_cfg is set with r top not inserted and r bottom equal to 0: v setpoint = 1.1v C 0.099v or 1.001v if odd values of output voltage are required from 0.5 v to 3.3v, use only the vout_cfg resistor divider, the v trim pin can be open or shorted to v dd25 . if the output set point is 5 v, the vout_cfg must have r top equal to 10k and r bottom equal to 23.2 k and vtrim_cfg must have r top equal to 20k and r bottom equal to 11k.
ltc3883/LTC3883-1 50 3883f a pplica t ions i n f orma t ion table 12. vout_cfg r top (k) r bottom (k) v out (v) 0 or open open nvm 10 23.2 see vtrim 10 15.8 3.3 16.2 20.5 3.1 16.2 17.4 2.9 20 17.8 2.7 20 15 2.5 20 12.7 2.3 20 11 2.1 24.9 11.3 1.9 24.9 9.09 1.7 24.9 7.32 1.5 24.9 5.76 1.3 24.9 4.32 1.1 30.1 3.57 0.9 30.1 1.96 0.7 open 0 0.5 table 13. vtrim_cfg r top (k) r bottom (k) v trim (mv) change to v set voltage v out (v) if v out has 10k/23.3k 0 or open open 0 nvm 10 23.2 99 nvm 10 15.8 86.625 nvm 16.2 20.5 74.25 nvm 16.2 17.4 61.875 nvm 20 17.8 49.5 nvm 20 15 37.125 5.5 20 12.7 24.75 5.25 20 11 12.375 5 24.9 11.3 C12.375 4.75 24.9 9.09 C24.75 4.5 24.9 7.32 C37.125 4.25 24.9 5.76 C49.5 4 24.9 4.32 C61.875 3.75 30.1 3.57 C74.25 3.63 30.1 1.96 C86.625 3.5 open 0 C99 3.46 table 14. freq_cfg (phase based on falling edge of sync) r top (k) r bottom (k) frequency (khz) sync to 0 description 0 or open open nvm nvm nvm 10 23.2 250 0 2-phase 10 15.8 250 120 3-phase 16.2 20.5 250 180 2-phase 16.2 17.4 425 0 2-phase 20 17.8 425 120 3-phase 20 15 425 180 2-phase 20 12.7 500 0 2-phase 24.9 11.3 500 180 2-phase 24.9 9.09 575 0 2-phase 24.9 7.32 575 120 3-phase 24.9 5.76 575 180 2-phase 24.9 4.32 650 0 2-phase 30.1 3.57 650 120 3-phase 30.1 1.96 650 180 2-phase open 0 external clock 0 2-phase
ltc3883/LTC3883-1 51 3883f a pplica t ions i n f orma t ion frequency and phase selection using rconfig the frequency and phase commands are linked if they are set using the rconfig pins. if pmbus commands are used the two parameters are independent. the sync pins must be shared in poly-phase configurations where multiple ltc3883s are used to produce the output. if the configuration is not polyphase the sync pins do not have to be shared. if the sync pins are shared between ltc3883s only one sync pin can be set as a frequency output, all other sync pins must be set to external clock. for example in a 2- phase configuration clocked at 425khz, one of the ltc3883s must be set to the desired frequency and phase and the other ltc3883 must be set to external clock. all phasing is with respect to the falling edge of sync. ltc3883 chip 1 set the frequency to 425 khz with 180 phase shift: r top = 20k and r bottom = 15k ltc3883 chip 2 set the frequency to external clock with 0 phase shift: r top = open and r bottom = 0 frequencies of 350khz, 750 khz and 1000 khz can only be set using nvm programming. if a 6- phase configuration is desired, nvm programming will give optimal phasing. all other configurations in frequency and phasing can be achieved using the freq_cfg pin. address selection using rconfig the ltc3883 address may be selected using a combination of the address stored in nvm and the asel pin. the three msbs of the device address are set by the three msbs stored in nvm, and four lsbs of the device address are set by the asel pin. this allows 16 different ltc3883s on a single board with one programmed address in nvm. if the address stored in nvm is 0 x4f, then the part address can be set from 0 x40 to 0 x4f using asel. ( the standard default address is 0 x4f). do not set any part address to 0x5a or 0 x5b because these are global addresses and all parts will respond to them. to choose address 0x40 r top is open and r bottom = 0 to choose address 0x45 r top = 24.9k and r bottom = 7.32k to choose address 0x4e r top = 10.0k and r bottom = 15.8k table 15. asel r top (k) r bottom (k) slave address lsb hex 0 or open open nvm 10 23.2 nvm (3msbs)_1111 f 10 15.8 nvm (3msbs)_1110 e 16.2 20.5 nvm (3msbs)_1101 d 16.2 17.4 nvm (3msbs)_1100 c 20 17.8 nvm (3msbs)_1011 b 20 15 nvm (3msbs)_1010 a 20 12.7 nvm (3msbs)_1001 9 20 11 nvm (3msbs)_1000 8 24.9 11.3 nvm (3msbs)_0111 7 24.9 9.09 nvm (3msbs)_0110 6 24.9 7.32 nvm (3msbs)_0101 5 24.9 5.76 nvm (3msbs)_0100 4 24.9 4.32 nvm (3msbs)_0011 3 30.1 3.57 nvm (3msbs)_0010 2 30.1 1.96 nvm (3msbs)_0001 1 open 0 nvm (3msbs)_0000 0 table 15a 1 . ltc3883 mfr_address command examples expressing both 7- or 8-bit addressing description hex device address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w 7 bit 8 bit rail 4 0x5a 0xb4 0 1 0 1 1 0 1 0 0 global 4 0x5b 0xb6 0 1 0 1 1 0 1 1 0 default 0x4f 0x9e 0 1 0 0 1 1 1 1 0 example 1 0x60 0xc0 0 1 1 0 0 0 0 0 0 example 2 0x61 0xc2 0 1 1 0 0 0 0 1 0 disabled 2,3,5 1 0 0 0 0 0 0 0 0 note 1: this table can be applied to the mfr_rail_address command as well as the mfr_address command. note 2: a disabled value in one command does not disable the device, nor does it disable the global address. note 3: a disabled value in one command does not inhibit the device from responding to device addresses specified in other commands. note 4: it is not recommended to write the value 0x00, 0x0c (7 bit), or 0x5a or 0x5b (7 bit) to the mfr_address or the mfr_rail_address commands. note 5: to disable the address enter 0x80 in the mfr_address command. the 0x80 is greater than the 7-bit address field, disabling the address.
ltc3883/LTC3883-1 52 3883f a pplica t ions i n f orma t ion e fficiency c onsiderations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: % efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc3883 circuits : 1) ic v in current , 2) intv cc regulator current , 3) i 2 r losses , 4) topside mosfet transition losses. 1. the v in current is the dc supply current given in the electrical characteristics table, which excludes mosfet driver and control currents. v in current typi- cally results in a small (<0.1%) loss. 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is a cur- rent out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. on the LTC3883-1, supplying extv cc from an output- derived source will scale the v in current required for the driver and control circuits by a factor of: v extvcc v in ? ? ? ? ? ? 1 efficiency ? ? ? ? ? ? for example, in a 20 v to 5 v application, 10ma of intv cc current results in approximately 2.5 ma of v in current. this reduces the mid-current loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 3. i 2 r losses are predicted from the dc resistances of the fuse ( if used), mosfet, inductor, current sense resistor. in continuous mode, the average output current flows through l and r sense , but is chopped between the topside mosfet and the synchronous mosfet. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l and r sense to ob- tain i 2 r losses. for example, if each r ds(on) = 10 m?, r l = 10 m?, r sense = 5 m?, then the total resistance is 25 m?. this results in losses ranging from 2% to 8% as the output current increases from 3 a to 15 a for a 5 v output, or a 3% to 12% loss for a 3.3 v output. efficiency varies as the inverse square of v out for the same external components and output power level. the combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. transition losses apply only to the topside mosfet(s), and become significant only when operating at high input voltages (typically 15 v or greater). transition losses can be estimated from: transition loss = (1.7) v in 2 i o(max) c rss f other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. it is very important to include these system level losses during the design phase. the internal battery and fuse resistance losses can be minimized by making sure that c in has ad- equate charge storage and very low esr at the switching frequency. a 25 w supply will typically require a minimum of 20 f to 40 f of capacitance having a maximum of 20 m? to 50 m? of esr. the ltc3883 2-phase architecture typically halves this input capacitance requirement over competing solutions. other losses including schottky con- duction losses during dead time and inductor core losses generally account for less than 2% total additional loss. c hecking t ransient r esponse the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive)
ltc3883/LTC3883-1 53 3883f a pplica t ions i n f orma t ion load current. when a load step occurs, v out shifts by an amount equal to ?i load ( esr), where esr is the effective series resistance of c out . ?i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recov- ery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. the availability of the i th pin not only allows optimization of control loop behavior but also provides a dc-coupled and ac-filtered closed-loop response test point. the dc step, rise time and settling at this test point truly reflects the closed loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the typical application circuit will provide an adequate starting point for most applications. the only two programmable parameters that affect loop gain are the voltage range, bits 5 and 6 of the mfr_pwm_ config_ltc3883 command and the current range, bit 7 of the mfr_pwm_mode_ lt c 3883 command. be sure to establish these settings prior to compensation calculation. the i th series r c -c c filter sets the dominant pole-zero loop compensation. the values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1 s to 10s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. placing a power mosfet with a resistor to ground directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce to a load step. the mosfet + r series will produce output currents approximately equal to v out /r series . r series values from 0.1 to 2 are valid depending on the current limit settings and the programmed output voltage. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the i th pin signal which is in the feedback loop and is the filtered and compensated control loop response. the gain of the loop will be in- creased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. a second, more severe transient is caused by switching in loads with large (>1 f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus a 10 f capacitor would require a 250 s rise time, limiting the charging current to about 200ma. polyphase configuration when configuring a polyphase rail with multiple ltc3883 s/ ltc3880s, the user must share the sync, ith, share_ clk, gpio, and alert pins of both parts. be sure to use pull- up resistors on gpio, share _ clk and alert . one of the part's sync pin must be set to the desired switching frequency, and all other frequency _ switch commands must be set to external clock. if an external oscillator is provided, set the frequency_switch command to external clock for all parts. the relative phasing of all the channels should be spaced equally. the mfr_rail_ address of all the devices should be set to the same value. when connecting a polyphase rail with ltc3883s, con- nect the v in pins of the 3883 s directly back to the supply voltage through the v in pin filter networks. refer to the typical application circuit: high efficiency 500 khz 2- phase 1.8v step-down converter with sense resistors.
ltc3883/LTC3883-1 54 3883f a pplica t ions i n f orma t ion when connecting a 3- phase ltc3883/ltc3880, the v in pin and power stage of the ltc3880 should be connected to the downstream side of the ltc3883 input current sense resistor. this allows the user to measure the total input current of the rail. refer to the typical application circuit: high efficiency 3-phase 350khz 1.8 v step-down converter with input current sense. the inductor dcr for all three inductors of ltc3883/ltc3880 application can be calculated. the dcr auto calibration routine can be performed on the ltc3883 phase by shutting down the other two phases. the dcr of the inductors of the ltc3880 phases can be calculated using the read_iin value of the ltc3883, and the mfr_read_iin of the ltc3880 phases. the user can shut down the other two phases and adjust the iout_cal_gain value of the respective ltc3880 phase so that the active phases mfr_read_iin = read_iin of the ltc3883. the user may also calibrate the dcr of all three inductors by only shutting down one phase at a time and leaving the other two phases active, however the dcr auto calibration routine cannot be used for the ltc3883 phase. the iout_cal_gain value of all the inductors should be set to the nominal drc value, dcr_nom prior to beginning the procedure. during the procedure, the circuit must be in a steady-state load condition, with the converter in ccm and sufficient load current to create a 6 mv average signal across the r iinsns sense resistor, as well as 6 mv across the output current sense network. first, the user needs to record the values of read_iin of the ltc3883 as well as the read_iout for all three phases. these values are referred to as read_ iin _a , read _ iout_1a , read _ iout_2a , and read_iout_3a. next, phase 1 should be shut off and the values for read_ iin of the ltc3883 and the read_iout for the two active phases need to be recorded. these values are referred to as read_iin_b, read_iout_2b, and read_iout_3b. to calculate the dcr of phase 1: verify that read_iin_a = read_iin_b the actual current of phase 1, iout_1a is calculated by: iout_1a = read_iin_a C read_iin_a ? {(read_iout_2a + read _iout_3a)/(read_ iout _2b + read_iout_3b) the actual dcr of the phase 1 inductor is calibrated to the correct value by: dcr_cal = dcr_nom ? (iout_1a/read_iout_a) the user then needs to update the iout_ cal_ gain command value with the calibrated value of inductor dcr, dcr_cal. the above procedure can then be repeated to determine the inductor dcr for phases 2 and 3. reference the subsection titled inductor dcr auto cali- bration in the applications information section for further detail regarding the operating conditions that must be met to accurately calculate the inductor dcr. pc b oard l a yout c hecklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. these items are also illustrated graphically in the layout diagram of figure 26. figure 27 illustrates the cur- rent waveforms present in the various branches of the synchronous regulator operating in the continuous mode. check the following in your layout: 1. is the top n-channel mosfet, m1, located within 1cm of c in ? 2. are ground and power ground kept separate? the com- bined ic ground pin and the ground return of c intvcc must return to the combined c out (C) terminals. the i th trace should be as short as possible. the path formed by the top n-channel mosfet, schottky diode and the c in capacitor should have short leads and pc trace lengths. the output capacitor (C) terminals should be connected as close as possible to the (C) terminals of the input ca- pacitor by placing the capacitors next to each other and away from the schottky loop described above. 3. are the i sense + and i sense C leads routed together with minimum pc trace spacing? the filter capacitor between i sense + and i sense C should be as close as possible to
ltc3883/LTC3883-1 55 3883f figure 26. recommended printed circuit layout diagram figure 27. branch current waveforms ltc3883 gnd i in_sns i sense + i sense ? v in v dd25 v dd33 i th v sense ? v sense + run sync tsns tg sw boost bg gnd intv cc v in_sns c1 r iin r iin v in r iinsns + q1 l m1 1f ceramic c b 3883 f26 c in + c intvcc m2 d1 c out v out r sense + c vin r vin r l d l sw r sense v out c out r sensein v in c in r in bold lines indicate high switching current. keep lines to a minimum length. current wavform at node 3883 f27 the ic. ensure accurate current sensing with kelvin connections at the sense resistor or inductor, whichever is used for current sensing. 4. is the intv cc decoupling capacitor connected close to the ic, between the intv cc and the power ground pins? this capacitor carries the mosfet driver current peaks. an additional 1 f ceramic capacitor placed immediately next to the intv cc and pgnd pins can help improve noise performance substantially. a pplica t ions i n f orma t ion 5. keep the switching node ( sw), top gate node ( tg), and boost node ( boost) away from sensitive small-signal nodes, especially from the voltage and current sensing feed-back pins. all of these nodes have very large and fast moving signals and therefore should be kept on the output side of the ltc3883 and occupy minimum pc trace area. if dcr sensing is used, place the top resistor (figure 18 a, r1) close to the switching node.
ltc3883/LTC3883-1 56 3883f a pplica t ions i n f orma t ion 6. use a modified star ground technique: a low imped- ance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the intv cc decoupling capacitor, the bottom of the voltage feedback resistive divider and the gnd pin of the ic. 7. are the v in_sns and i in_sns filters kelvin connected to the r sensein sense resistor? this will prevent the pcb trace resistance from causing errors in the input current measurement. these traces should be as short as possible and routed away from any noisy nodes such as the switching or boost nodes. 8. is the v in filter kelvin connected to the input side of the r sensein resistor? this can help improve the noise performance of the input current sense amplifier by reducing the voltage transients between the amplifier inputs and amplifier supply caused by the discontinuous power stage current. pc b oard l a yout d ebugging it is helpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit. monitor the output switching node ( sw pin) to synchronize the oscil- loscope to the internal oscillator a nd probe the actual output voltage as well. check for proper performance over the oper - ating voltage and current range expected in the application . the frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation thresholdtypically 10% of the maximum designed cur- rent level in burst mode operation. the duty cycle percentage should be maintained from cycle to cycle in a well- designed, low noise pcb implementation. variation in the duty cycle at a subharmonic rate can sug- gest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. overcompensation of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the un- dervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation. investigate whether any problems exist only at higher out- put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw , tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are encountered with high current output loading at lower input voltages, look for inductive coupling between c in , schottky and the top mosfet components to the sensitive current and voltage sensing traces. in addition, investigate common ground path voltage pickup between these components and the gnd pin of the ic. d esign e xample as a design example for a medium current regulator, as- sume v in = 12 v nominal, v in = 20 v maximum, v out = 3.3v, i max = 15a and f = 500khz (see figure 28). the regulated output is established by the vout_ command stored in nvm or placing the following resis- tor divider between vdd25 the rconfig pin and sgnd: 1. vout_cfg, r top = 10k, r bottom = 15.8 k 2. vtrim_cfg, open the frequency and phase are set by nvm or by setting the resistor divider between vdd25 freq_cfg and gnd with r top = 20 k and r bottom = 12.7 k. the address is set to xf where x is the msb stored in nvm. the following parameters are set as a percentage of the output voltage if the resistor configuration pins are used to determined output voltage: n vout _ o v _ fault _ limit .................................... +1 0% n vout _ o v _ warn _ limit .................................. + 7. 5% n vout _ ma x ....................................................... +7. 5% n vout _ m argin _ high ......................................... + 5% n power _ go od _ on ............................................. C 7% n power _ go od _off ............................................ C 8% n vout _ m argin _ low .......................................... C 5% n vout _ u v _ warn _ limit .................................. C6.5% n vout _ u v _ fault _ limit ...................................... C 7%
ltc3883/LTC3883-1 57 3883f gnd 0.1f 1f 10f v in 6v to 20v 5m 10k 2200pf 6.04k 22f 50v + d4 m1 m2 2.2k v out 3.3v 15a c out 530f 6v 3883 f28 10nf c out : 330h sanyo 4tpf330ml, 2 100f avx 12106d107kat2a l: coilcraft xpl7070 1h m1: renesas rjk0305dpb m2: renesas rjk0330dpb 1.0f 1.0f 0.2f 1.0h tg bg pgnd freq_cfg i in_sns boost v in_sns pgood v in sw intv cc ltc3883 10k gpio 10k sync 10k sda 10k pmbus interface v dd33 scl v out_cfg v trim_cfg asel wp i sense + i sense ? v sense + v sense ? v dd25 v dd33 tsns i th 10k alert 10k run 5k share_clk mmbt3906 100 100 1f 10nf 10nf 10f 3 figure 28. high efficiency 500khz 3.3v step-down converter a pplica t ions i n f orma t ion all other user defined parameters must be programmed into the nvm. the gui can be utilized to quickly set up the part with the desired operating parameters. the inductance values are based on a 35% maximum ripple current assumption (5.25 a). the highest value of ripple current occurs at the maximum input voltage: l = v out f ? ? i l(max) 1? v out v in(max) ? ? ? ? ? ? ? ? the controller will require 1.05 h. the nearest standard value is 1h. at the nominal input the ripple will be: ? i l(nom) = v out f ? l 1? v out v in(nom) ? ? ? ? ? ? ? ? the ripple will be 4.79 a (32%). the peak inductor current will be the maximum dc value plus one-half the ripple current or 17.39 a. the minimum on time occurs at the maximum v in , and should not be less than 90ns: t on(min) = v out v in(max) ? f = 1.8v 20v 500khz ( ) = 180ns the vishay ihlp 4040 dz -11 1 h (2.3 m dcr typ at 25 c) is the chosen inductor . assuming the temperature measurement of the inductor temperature is accurate and c1 is set to 0.2 f, r d is infinite and removed from the equations. r1 = l dcr at 25 c ( ) ? c1 = 1h 2.5m ? 0.2f = 1.37k
ltc3883/LTC3883-1 58 3883f the maximum power loss in r0 is related to the duty cycle, and will occur in continuous mode at the maximum input voltage: p loss r1 = v in(max) ? v out ( ) ? v out r1 = 20 ? 1.8 ( ) ? 1.8 1.37k = 23.91mw the current limit will be set 20% higher than the peak value to assure variation in components and noise in the system do not limit the average current. v ilimit = i peak ? r dcr(max) = 17.39 a ? 2.5m = 43mv the closest v ilimit setting is 42.9mv or 46.4 mv. the values are entered with the iout_oc_fault_limit command. based on expected variation and measurement in the lab across the sense capacitor the user can determine the optimal setting. the power dissipation on the topside mosfet can be eas- ily estimated. choose a renesas rjk0305dpb topside mosfet. r ds(on) = 10 m, c miller = 75 pf. at maximum input voltage with t estimated = 50 c and a bottom side mosfet a renesas rjk0330dpb, r ds(on) = 3m: p main = 1.8v 20v ? 17.25 ( ) 2 ? 1 + 0.005 ( ) 50 c ? 25 c ( ) ? ? ? ? ? 0.01 + 20v ( ) 2 8.695a ( ) ? 1 5 ? 2.3 + 1 2.3 ? ? ? ? ? ? 75pf ( ) 500khz ( ) = 0.406w the loss in the bottom side mosfet is: p sync = 20v ? 1.8v ( ) 20v ? 17.25a ( ) 2 ? 1 + 0.005 ( ) 50 c ? 25 c ( ) ? ? ? ? ? 0.003 = 0.913w both mosfets have i 2 r losses while the p main equation includes an additional term for transition losses, which are highest at high input voltages. a pplica t ions i n f orma t ion c in is chosen for an rms current rating of: c in required i rms = 17.25 20 1.8 ( ) ? 20 ? 1.8 ( ) ? ? ? ? 1/2 = 4.9a at temperature. c out is chosen with an esr of 0.006 for low output ripple. the output ripple in continuous mode will be highest at the maximum input voltage. the output voltage ripple due to esr is v oripple = r(?i l ) = 0.006 ? 5.5a = 33mv. c onnecting the usb to i 2 c/smbus/pmbus c ontroller to the ltc3883 i n s ystem the lt c usb to i 2 c/smbus/pmbus controller can be interfaced to the ltc3883 on the users board for pro- gramming, telemetry and system debug. the controller, when used in conjunction with ltpowerplay, provides a powerful way to debug an entire power system. faults are quickly diagnosed using telemetry, fault status commands and the fault log. the final configuration can be quickly developed and stored to the ltc3883 eeprom. figure 29 illustrates the application schematic for powering, programming and communication with one or more ltc3883s via the ltc i 2 c/smbus/pmbus controller regardless of whether or not system power is present. if system power is not present the dongle will power the ltc3883 through the v dd33 supply pin. to initialize the part when v in is not applied and the v dd33 pin is powered use global address 0 x5b command 0 xbd data 0x2b followed by address 0 x5b command 0 xbd data 0xc4. the part can now be communicated with, and the project file updated. to write the updated project file to the nvm issue a store_ user_ all command. when vin is applied, a mfr_reset must be issued to allow the pwm to be enabled and valid adcs to be read. because of the controllers limited current sourcing capabil- ity, only the ltc3883s, their associated pull-up resistors and the i 2 c pull-up resistors should be powered from the ored 3.3 v supply. in addition any device sharing the i 2 c bus connections with the ltc3883 should not have body diodes between the sda/scl pins and their respective
ltc3883/LTC3883-1 59 3883f figure 29. lt c controller connection a pplica t ions i n f orma t ion v dd node because this will interfere with bus communica- tion in the absence of system power. if v in is applied the dongle will not supply the ltc3883s on the board. it is recommended the run pins be held low to avoid providing power to the load until the part is fully configured. the lt c controller i 2 c connections are optoisolated from the pc usb. the 3.3 v from the controller and the ltc3883 v dd33 pin must be driven to each ltc3883 with a separate pfet. if v in is not applied, the v dd33 pins can be in parallel because the on-chip ldo is off. the controller 3.3 v cur- rent limit is 100 ma but typical v dd33 currents are under 15ma. the v dd33 does back drive the intv cc /extv cc pin. normally this is not an issue if v in is open. i nductor dcr a uto c alibra tion using the dc resistance of the inductor as a current shunt element has several advantagesno additional power loss, lower circuit complexity and cost. however any error between the specified nominal inductor dcr value and the actual dcr value will cause a proportional error in the peak current limit, as well as the output current read-back value. the ltc3883 can calibrate the inductor dcr value to compensate for the tolerance from its typical value. setting bit 3 of the mfr_pwm_mode_3883 command will start the calibration procedure. to successfully complete the calibration procedure, the pwm must be enabled, the duty_cycle value must be at least 3%, the read_iin value must be at least 10 ma, and the calibrated iout_cal_gain must be with 30% of the uncalibrated iout_cal_gain value. if any of the above conditions are not met, bit 0 of the status_cml command will be set, and the value of iout_cal_gain will not be changed. during the inductor dcr calibration the supply voltage, output voltage, and load current must be in a steady state condition for 180 ms during the command execution to ensure accurate calibration. the load current should be sufficiently large to create at least a 6 mv average signal across the r iinsns sense resistor as well as 6 mv across the output current sense network in order to ensure that the read_iin and read_iout values used in the dcr calibration calculation are within 1% tue. the inductor dcr is calibrated by multiplying the measured read_iin value by the measured read_ duty_ cycle value to obtain a calculated output current. the ltc3883 then updates the iout_cal_gain value so that the measured read_iout value matches the calculated output current value that is based on power stage input current and duty cycle, so that read_iout ? duty_cycle = read_iin. v in v in v dd33 v dd25 sda 1f 1f vgs max on the tp0101k is 8v if v in > 16v change the resistor divider on the pfet gate 1f 1f 3883 f29 10k 100k tp0101k isolated 3.3v sda scl tp0101k 100k lt c controller header to ltc dc1613 usb to i 2 c/smbus/pmbus controller scl wp sgnd ltc3883 v in v dd33 sda scl wp sgnd ltc3883 10k v dd25
ltc3883/LTC3883-1 60 3883f a pplica t ions i n f orma t ion a ccurate dcr t emperature c ompensation using the dc resistance of the inductor as a current shunt element has several advantagesno additional power loss, lower circuit complexity and cost. however, the strong temperature dependence of the inductor resistance and the difficulty in measuring the exact inductor core temperature introduce errors in the current measurement. for copper, a change of inductor temperature of only 1c corresponds to approximately 0.39% current gain change . figure 30 shows a dc/dc converter sample layout (right) and its corresponding thermal image ( left). the converter is providing 1.8v, 1.5a to the output load. heat dissipation in the inductor under high load condi- tions creates transient and steady state thermal gradients between the inductor and the temperature sensor, and the sensed temperature does not accurately represent the inductor core temperature. this temperature gradient is clearly visible in the thermal image of figure 30. in addition, transient heating/cooling effects have to be accounted for in order to reduce the transient errors introduced when load current changes are faster than heat transfer time constants of the inductor. both of these problems are addressed by introducing two additional parameters: the thermal resistance is from the inductor core to the on- board temperature sensor, and the inductor thermal time constant . the thermal resistance is [ c/w], is used to calculate the steady-state difference between the sensed temperature t s and the internal inductor temperature t i for a given power dissipated in the inductor p i : t i C t s = is p i = is v dcr i out the additional temperature rise is used for a more accurate estimate of the inductor dc resistance r i : r i = r0 (1 + a [t s C t ref + is v dcr i out ]) in the equations above, v dcr is the inductor dc voltage drop, i out is the rms value of the output current, r0 is the inductor dc resistance at the reference temperature t ref and a is the temperature coefficient of the resistance. since most inductors are made of copper, we can expect a temperature coefficient close to a cu = 3900ppm/c. for a given a , the remaining parameters is and r0 can be calibrated at a single temperature using only two load currents: ro = r2 ?r1 ( ) p2 + p1 ( ) ? r2 + r1 ( ) p2 ?p1 ( ) t2 ? t1 ( ) p2 + p1 ( ) ? p2 ?p1 ( ) 2 + t1 + t2 ? 2t ref [ ] ( ) is = 1 ro ? r1 + r2 ( ) t2 ? t1 ( ) ? r2 ?r1 ( ) 2 + t1 + t2 ? 2t ref [ ] ( ) t2 ? t1 ( ) p2 + p1 ( ) ? p2 ?p1 ( ) 2 + t1 + t2 ? 2t ref [ ] ( ) the inductor resistance, r k = v dcr(k) /i out(k) , power dis- sipation p k = v dcr(k) i out(k) and the sensed temperature t k , (k = 1, 2) are recorded for each load current. to increase figure 30. thermal image and layout photo dc/dc converter 3883 f30 inductor temperature sensor
ltc3883/LTC3883-1 61 3883f a pplica t ions i n f orma t ion the accuracy in calculating is , the two load currents should be chosen around i 1 = 10% and i 2 = 90% of the current range of the system. the inductor thermal time constant models the first order thermal response of the inductor and allows accurate dcr compensation during load transients. during a transition from low-to-high load current, the inductor resistance increases due to the self-heating. if we apply a single load step from the low current i 1 to the higher current i 2 , the voltage across the inductor will change instantaneously from i 1 r1 to i 2 r1 and then slowly approach i 2 r2. here r1 is the steady-state resistance at the given temperature and load current i 1 , and r2 is the slightly higher dc resistance at i 2 , due to the inductor self-heating. note that the electri- cal time constant el = l/r is several orders of magnitude shorter than the thermal one, and instantaneous is rela- tive to the thermal time constant. the two settled regions give us the data sets ( i 1 , t1, r1, p1) and ( i 2 , t2, r2, p2) and the 2- point calibration technique (1.3-1.4) is used to extract the steady-state parameters is and r 0 ( given a previously characterized average a ). the relative current error calculated using the steady-state expression (1.2) will peak immediately after the load step, and then decay to zero with the inductor thermal time constant . ? i i t ( ) = is v2i 2 ? v1i 1 ( ) e ? t/ the time constant is calculated from the slope of the best-fit line y = ln(?i/i) = a1 + a2t: = ? 1 a2 in summary, a single load current step is all that is needed to calibrate the dcr current measurement. the stable por- tions of the response give us the thermal resistance is and nominal dc resistance r0, and the settling characteristic is used to measure the inductor thermal time constant . to get the best performance, the temperature sensor has to be as close as possible to the inductor and away from other significant heat sources. for example in figure 30, the bipolar sense transistor is close to the inductor and away from the switcher. connecting the collector of the pnp to the local power ground plane assures good thermal contact to the inductor, while the base and emitter should be routed to the ltc3883 separately, and the base con- nected to the signal ground close to ltc3883. ltpowerplay: a n i nteractive gui for d igit al p ower ltpowerplay is a powerful windows-based development environment that supports linear technology digital power ics including the ltc3883. the software supports a variety of different tasks. ltpowerplay can be used to evaluate linear technology ics by connecting to a demo board or the user application. ltpowerplay can also be used in an offline mode ( with no hardware present) in order to build multiple ic configuration files that can be saved and re-loaded at a later time. ltpowerplay provides unprecedented diagnostic and debug features. it becomes a valuable diagnostic tool during board bring-up to pro- gram or tweak the power system or to diagnose power issues when bring up rails. ltpowerplay utilizes linear technology s usb- to -i 2 c/ smbus/ pmbus controller to communication with one of the many potential targets including the dc1778a demo board, the dc1890a sock- eted programming board, or a customer target system. the software also provides an automatic update feature to keep the revisions current with the latest set of device drivers and documentation. a great deal of context sen- sitive help is available with ltpowerplay along with sev- eral tutorial demos. complete information is available at http://www.linear.com/ltpowerplay. pmbus c ommunica tion and c ommand p rocessing the ltc3883/LTC3883-1 have a one deep buffer to hold the last data written for each supported command prior to processing as shown in figure 32; write command data processing. when the part receives a new command from the bus, it copies the data into the write command data buffer, indicates to the internal processor that this command data needs to be fetched, and converts the command to its internal format so that it can be executed. tw o distinct parallel blocks manage command buffering and command processing ( fetch, convert, and execute) to ensure the last data written to any command is never lost.
ltc3883/LTC3883-1 62 3883f a pplica t ions i n f orma t ion figure 33. example of a command write of vout_command command data buffering handles incoming pmbus writes by storing the command data to the write command data buffer and marking these commands for future process- ing. the internal processor runs in parallel and handles the sometimes slower task of fetching, converting and executing commands marked for processing. some computationally intensive commands ( e.g., timing parameters, temperatures, voltages and currents) have // wait until bits 6, 5, and 4 of mfr_common are all set do { mfrcommonvalue = pmbus_read_byte(0xef); partready = (mfrcommonvalue & 0x70) == 0x70; }while(!partready) figure 31. ltpowerplay screen shot decoder cmd internal processor write command data buffer page cmds 0x00 0x21 0xfd 3883 f32 x1 ? ? ? ? ? ? mfr_reset vout_command s calculations pending pmbus write r fetch, convert data and execute data mux figure 32. write command data processing internal processor execution times that may be long relative to pmbus timing. if the part is busy processing a command, and new command(s) arrive, execution may be delayed or processed in a different order than received. the part indicates when internal calculations are in process via bit ?5 of mfr_common ( calculations not pending). when the part is busy calculating, bit 5 is cleared. when this bit is set, the part is ready for another command. an example polling loop is provided in figure 33 which ensures that commands are processed in order while simplifying error handling routines.
ltc3883/LTC3883-1 63 3883f a pplica t ions i n f orma t ion fault/ alert notification. the part can nack commands for other reasons, however, as required by the pmbus spec (for instance, an invalid command or data). an example of a robust command write algorithm for the vout_ command register is provided in figure 31. it is recommended that all command writes ( write byte, write word, etc.) be preceded with a polling loop to avoid the extra complexity of dealing with busy behavior and unwanted alertb notification. a simple way to achieve this is to create a safe_ write_ byte() and safe_ write_ word() subroutine. the above polling mechanism allows your software to remain clean and simple while robustly communicating with the part. for a detailed discussion of these topics and other special cases please refer to the application note tbd implementing robust pmbus system software located at www. linear. com/ designtools/ app_notes. when communicating using bus speeds at or below 100khz, the polling mechanism shown here provides a simple solution that ensures robust communication without clock stretching. at bus speeds in excess of 100 khz, it is strongly recommended that the part be configured to en- able clock stretching. this requires a pmbus master that supports clock stretching. system software that detects and properly recovers from the standard pmbus nack/ busy faults as described in the pmbus specification v1.1, part ii, section 10.8.7 is required to communicate above 100khz without clock stretching. when the part receives a new command while it is busy, it will communicate this condition using standard pmbus protocol. depending on part configuration it may either nack the command or return all ones (0 xff) for reads. it may also generate a busy fault and alert notification, or stretch the scl clock low. for more information refer to pmbus specification v1.1, part ii, section 10.8.7 and smbus v2.0 section 4.3.3. clock stretching can be enabled by asserting bit 1 of mfr_config_all_ lt c 3883. clock stretching will only occur if enabled and the bus com- munication speed exceeds 100khz. pmbus busy protocols are well accepted standards, but can make writing system level software somewhat com- plex. the part provides three hand shaking status bits which reduce complexity while enabling robust system level communication. the three hand shaking status bits are in the mfr_ common command. when the part is busy executing an internal operation, it will clear bit 6 of mfr_ common (chip not busy). when the part is busy specifically because it is in a transitional v out state ( margining hi/lo, power off/ on, moving to a new output voltage set point, etc.) it will clear bit 4 of mfr_common ( output not in transition). when internal calculations are in process, the part will clear bit ?5 of mfr_ common (calculations not pending). these three status bits can be polled with a pmbus read byte of the mfr_common command until all three bits are set. a command immediately following the status bits being set will be accepted without nacking or generating a busy
ltc3883/LTC3883-1 64 3883f pmb us c omman d de t ails a ddressing and w rite p rotect command name cmd code description type d ata format units nvm default value page 0x00 provides integration with multi-page pmbus devices. r/w byte reg 0x00 write_protect 0x10 level of protection provided by the device against accidental changes. r/w byte reg y 0x00 mfr_address 0xe6 sets the 7-bit i 2 c address byte. r/w byte reg y 0x4f mfr_rail_address 0 xfa common address for polyphase outputs to adjust common parameters. r/w byte reg y 0x80 page the ltc3883 only supports a page value of 0 x00 or 0 xff. any other value will generate a cml fault. the page com- mand is included to provide integration with multi-page pmbus devices. there are no restrictions as to what commands can be written or read when page is set to 0xff. write_protect the write_protect command is used to control writing to the ltc3883 device. this command does not indicate the status of the wp pin which is defined in the mfr_common command. the wp pin takes precedence over the value of this command unless the write_protect command is more stringent. byte meaning 0x80 disable all writes except to the write_protect, page, mfr_ ee_unlock, and store_user_all command. 0x40 disable all writes except to the write_protect, page, mfr_ee_unlock, mfr_clear_peaks, store_user_all, operation and clear_faults command. individual fault bits can be cleared by writing a 1 to the respective bits in the status commands. 0x20 disable all writes except to the write_protect, operation, mfr_ee_unlock, mfr_clear_peaks, clear_faults, page, on_off_config, vout_command and store_user_ all. individual fault bits can be cleared by writing a 1 to the respective bits in the status commands. 0x10 reserved, must be 0 0x08 reserved, must be 0 0x04 reserved, must be 0 0x02 reserved, must be 0 0x01 reserved, must be 0 enable writes to all commands when write_protect is set to 0x00. if wp pin is high, page, operation, mfr _ clear_ peaks, mfr _ ee_ unlock, write _ protect and clear_ faults commands are supported. individual fault bits can be cleared by writing a 1 to the respective bits in the status commands.
ltc3883/LTC3883-1 65 3883f mfr_address the mfr_address command byte sets the 7 bits of the pmbus slave address for this device. setting this command to a value of 0 x80 disables device addressing. the global device address, 0 x5a and 0x5b, cannot be deactivated. if rconfig is set to ignore, the asel pin is still used to determine the lsb of the channel ad- dress. if the asel pin is open, the ltc3883 will use the address value stored in nvm. this command has one data byte. mfr_rail_address the mfr_rail_address command enables direct device address access to the page activated channel. the value of this command should be common to all devices attached to a single power supply rail. the user should only perform command writes to this address. if a read is performed from this address and the rail devices do not respond with exactly the same value, the ltc3883 will detect bus contention and may set a cml communications fault. setting this command to a value of 0x80 disables rail device addressing for the channel. this command has one data byte. g eneral c onfigura tion commands command name cmd code description type d ata format units nvm default value mfr_chan_config_ lt c 3883 0xd0 configuration bits that are channel specific. r/w byte reg y 0x1f mfr_config_all_ lt c 3883 0xd1 general configuration bits. r/w byte reg y 0x09 mfr_chan_config_ ltc 3883 general purpose configuration command common to multiple lt c products. bit meaning 7 reserved 6 reserved 5 reserved 4 disable run low. when asserted the run pin is not pulsed low if commanded off 3 short cycle. when asserted the output will immediate off if commanded on while waiting for toff_delay or toff_fall. toff_min of 120ms is honored then the part will command on. 2 share_clock control. if share_clock is held low, the output is disabled 1 no gpio alert, alert is not pulled low if gpio is pulled low externally. assert this bit if either power_good or vout_uvuf are propagated on gpio. 0 disables the vout decay value requirement for mfr_retry_time processing. when this bit is set to a 0, the output must decay to less than 12.5% of the programmed value for any action that turns off the rail including a fault, an off/on command, or a toggle of run from high to low to high. this command has one data byte. pmb us c omman d de t ails
ltc3883/LTC3883-1 66 3883f mfr_config_all_ ltc 3883 general purpose configuration command common to multiple lt c products bit meaning 7 enable fault logging 6 ignore resistor configuration pins 5 reserved 4 reserved 3 mask pll unlock fault 2 a valid pec required for pmbus writes to be accepted. if this bit is not set, the part will accept commands with invalid pec. 1 enable the use of pmbus clock stretching 0 reserved this command has one data byte. o n /o ff /m argin command name cmd code description type d ata format units nvm default value on_off_config 0x02 run pin and pmbus bus on/off command configuration. r/w byte reg y 0x1e operation 0x01 operating mode control. on/off, margin high and margin low. r/w byte reg y 0x80 mfr_reset 0xfd commanded reset without requiring a power-down. send byte na on_off_config the on_off_config command configures the combination of run pin input and serial bus commands needed to turn the unit on and off. this includes how the unit responds when power is applied. the only bits allowed to be changed are as follows: 3: controls how the unit responds to commands received via the serial bus 0: run pin action when commanding the unit to turn off. if bit 0 is set to one, the part will stop transferring power to the output stage as fast as possible. this will have the effect of the load discharging the output capacitor. setting bit 0 to a zero will cause the regulator to use the programmed turn-off delay and fall times. if the part is in continu- ous mode, the programmed turn-off response may pull the output to zero volts considerably faster than removing power immediately from the load. changing the value of bits 4, 2 or 1, will generate a cml fault. this command has one data byte. pmb us c omman d de t ails
ltc3883/LTC3883-1 67 3883f table 3. on_off_config detailed command information on_off_config data contents bits (s) symbol operation b[7:5] reserved dont care. always returns 0. b[3] on_off_config_use_pmbus controls how the unit responds to commands received via the serial bus. 0: unit ignores the operation command b[7:6]. 1: unit responds to operation command b[7:6]. the unit also requires the run pin to be asserted for the unit to start. b[0] on_off_config_control_fast_off run pin turn off action when commanding the unit to turn off. 0: use the programmed toff_delay. 1: turn off the output and stop transferring energy as quickly as possible. the device does not sink current in order to decrease the output voltage fall time. note: a high on the run pin is always required to start power conversion. power conversion will always stop with a low on run. operation the operation command is used to turn the unit on and off in conjunction with the input from the run pin. it is also used to cause the unit to set the output voltage to the upper or lower margin voltages. the unit stays in the commanded operating mode until a subsequent operation command or change in the state of the run pin instructs the device to change to another mode. if the part is stored in the margin_low/high state, the next reset or power_on cycle will ramp to that state. if the operation command is modified, for example on is changed to margin_low, the output will move at a fixed slope set by the vout_transition_rate. margin high (ignore faults) and margin low (ignore faults) operations are not supported by the ltc3883. the part defaults to the on state. this command has one data byte. table 4. operation command detail command operation data contents when on_off_config_use_pmbus enables operation_control symbol action value bits function turn off immediately 0x00 turn on 0x80 margin low 0x98 margin high 0xa8 sequence off 0x40 operation data contents when on_off_config is configured such that operation command is not used to command channel on or off symbol action value bits function output at nominal 0x80 margin low 0x98 margin high 0xa8 note: attempts to write a reserved value will cause a cml fault. pmb us c omman d de t ails
ltc3883/LTC3883-1 68 3883f mfr_reset this command provides a means by which the user can perform a reset of the ltc3883. this write-only command has no data bytes. pwm c onfigura tion command name cmd code description type d ata format units nvm default value mfr_pwm_mode_ lt c 3883 0xd4 configuration for the pwm engine. r/w byte reg y 0xd2 mfr_pwm_config_ lt c 3883 0xf5 set numerous parameters for the dc/dc controller including phasing. r/w byte reg y 0x10 frequency_switch 0x33 switching frequency of the controller. r/w word l11 khz y 350 0xfabc mfr_pwm_mode_ ltc 3883 the mfr_ pwm_ mode_ lt c 3883 command allows the user to program the pwm controller to use burst mode operation , discontinuous (pulse-skipping mode), or forced continuous conduction mode. bit meaning 7 0b 1b use high range of i limit low current range high current range 6 enable servo mode [5:4] 00b 01b 10b read_iin gain setting 2x gain, 50mv max input 4x gain, 20mv max input 8x, gain, 8mv max input 3 start dcr auto calibration 2 reserved bit[1:0] 00b 01b 10b mode discontinuous burst mode operation forced continuous whenever the channel is ramping on, the pwm mode will be discontinuous, regardless of the value of this command. bit [7] of this command determines if the part is in high range or low range of the iout_oc_fault_limit command. changing this bit value changes the pwm loop gain and compensation. changing this bit value whenever an output is active may have detrimental system results. bit [6] the ltc3883 will not servo while the part is off, ramping on or ramping off. when set to a one, the output servo is enabled. the output set point dac will be slowly adjusted to minimize the difference between the read_vout_adc and the vout_command (or the appropriate margined value). bit[5:4] set the read_iin gain and range setting of the input current sense amplifier. pmb us c omman d de t ails
ltc3883/LTC3883-1 69 3883f bit[3] setting this bit to a 1 starts the patent pending inductor dcr auto calibration to determine the dcr of the inductor. this will update the value of iout_cal_gain using the read_iin, read_iout, and duty_cycle values. iout_cal_gain is adjusted so that read_iout ? duty_cycle = read_iin. the auto calibration procedure will only complete successfully if the following conditions are met. 1) the pwm is enabled 2) duty_cycle is at least 3% 3) read_iin is at least 10ma 4) the calibrated iout_cal_gain is within 30% of the uncalibrated iout_cal_gain if any of the above conditions are not met, bit 0 of the status_cml command will be set, and the value of iout_ cal_gain will not be changed. bit[3] must then be reset to a 0 by the user. a store_user_all command must be issued to store the updated iout_cal_gain value into nvm. bit[1:0] determine the pwm mode of operation. this command has one data byte. mfr_pwm_config_ ltc 3883 the mfr_pwm_config_ lt c 3883 command sets the switching frequency and phase offset with respect to the falling edge of the sync signal. the part must be in the off state to process this command. the run pin must be low or the part must be commanded off. if the part is in the run state and this command is written, the command will be ignored and a busy fault will be asserted. bit 6 of this command affects the loop gain of the pwm output which may require modifications to the external compensation network. bit meaning 7 reserved, set to 0. 6 if v out range = 1, the maximum output voltage is 2.75v. if range = 0, the maximum output voltage is 5.5v. 5 reserved 4 share clock enable : if this bit is 1, the share_clk pin will not be released until v in > vin_on. the share_clk pin will be pulled low when v in < vin_off. if this bit is 0, the share_clk pin will not be pulled low when vin < vin_off except for the initial application of vin. 3 reserved, set to 0 bit [2:0] phase offset 000b 0 001b 90 010b 180 011b 270 100b 60 101b 120 110b 240 111b 300 this command has one data byte. pmb us c omman d de t ails
ltc3883/LTC3883-1 70 3883f pmb us c omman d de t ails frequency_switch the frequency_switch command sets the switching frequency, in khz, of a pmbus device. supported frequencies: value [15:0] resulting frequency ( typ ) 0x0000 external oscillator 0xf3e8 250khz 0xfabc 350khz 0xfb52 425khz 0xfbe8 500khz 0x023f 575khz 0x028a 650khz 0x02ee 750khz 0x03e8 1000khz the part must be in the off state to process this command. the run pin must be low or the part must be commanded off. if the part is in the run state and this command is written, the command will be ignored and a busy fault will be asserted. when the part is commanded off and the frequency is changed, a pll_unlock status may be detected as the pll locks onto the new frequency. this command has two data bytes and is formatted in linear_5s_11s format. v ol tage input v oltage and limits command name cmd code description type d ata format units nvm default value vin_ov_fault_ limit 0x55 input supply overvoltage fault limit. r/w word l11 v y 15.5 0xd3e0 vin_uv_warn_limit 0x58 input supply undervoltage warning limit. r/w word l11 v y 6.3 0xcb26 vin_on 0x35 input voltage at which the unit should start power conversion. r/w word l11 v y 6.5 0xcb40 vin_off 0x36 input voltage at which the unit should stop power conversion. r/w word l11 v y 6.0 0xcb00 mfr_rvin 0xf7 the resistance value of the v in pin filter element in milliohms r/w word l11 m y 3000 0x12ee vin_ov_fault_limit the vin_ov_fault_limit command sets the value of the measured input voltage, in volts, that causes an input overvoltage fault. the fault is detected with the a/d converter resulting in latency up to 120ms. this command has two data bytes and is formatted in linear_5s_11s format. vin_uv_warn_limit the vin_uv_warn_limit command sets the value of the input voltage that causes an input undervoltage warning. the warning is detected with the a/d converter resulting in latency up to 120ms. this command has two data bytes and is formatted in linear_5s_11s format.
ltc3883/LTC3883-1 71 3883f vin_on the vin_on command sets the input voltage, in volts, at which the unit should start power conversion. this command has two data bytes and is formatted in linear_5s_11s format. vin_off the vin_off command sets the input voltage, in volts, at which the unit should stop power conversion. this command has two data bytes and is formatted in linear_5s_11s format. mfr_rvin the mfr_rvin command is used to set the resistance value of the v in pin filter element in milliohms . ( see also read_vin). set mfr_rvin equal to 0 if no filter element is used. this command has two data bytes and is formatted in linear_5s_11s format. output voltage and limits command name cmd code description type d ata format units nvm default value vout_mode 0x20 output voltage format and exponent (2 C12 ). r byte reg 2 C12 0x14 vout_max 0x24 upper limit on the output voltage the unit can command regardless of any other commands. r/w word l16 v y 5.5 0x5800 vout_ov_fault_ limit 0x40 output overvoltage fault limit. r/w word l16 v y 1.1 0x119a vout_ov_warn_ limit 0x42 output overvoltage warning limit. r/w word l16 v y 1.075 0x1133 vout_margin_high 0x25 margin high output voltage set point. must be greater than vout_command. r/w word l16 v y 1.05 0x10cd vout_command 0x21 nominal output voltage set point. r/w word l16 v y 1.0 0x1000 vout_margin_low 0x26 margin low output voltage set point. must be less than vout_command. r/w word l16 v y 0.95 0x0f33 vout_uv_warn_ limit 0x43 output undervoltage warning limit. r/w word l16 v y 0.925 0x0ecd vout_uv_fault_ limit 0x44 output undervoltage fault limit. r/w word l16 v y 0.9 0x0e66 power_good_on 0x5e output voltage at or above which a power good should be asserted. r/w word l16 v y 0.93 0x0ee1 power_good_ off 0 x5f output voltage at or below which a power good should be de-asserted. r/w word l16 v y 0.92 0x0eb8 mfr_vout_max 0xa5 maximum allowed output voltage. r word l16 v 5.5 0x5800 vout_mode the data byte for vout_mode command, used for commanding and reading output voltage, consists of a 3- bit mode (only linear format is supported) and a 5- bit parameter representing the exponent used in output voltage read/write commands. this read-only command has one data byte. pmb us c omman d de t ails
ltc3883/LTC3883-1 72 3883f pmb us c omman d de t ails vout_max the vout_max command sets an upper limit on the output voltage, in volts, the unit can command regardless of any other commands or combinations. this command has two data bytes and is formatted in linear_16u format. vout_ov_fault_limit the vout_ov_fault_limit command sets the value of the output voltage measured at the sense pins, in volts, which causes an output overvoltage fault. if the vout_ov_fault_limit is modified and the part is in the run state, allow 10 ms after the command is modified to assure the new value is being honored. the part indicates if it is busy making a calculation. monitor bits 5 and 6 of mfr_common. either bit is low if the part is busy. if this wait time is not met, and the vout_command is modified above the old overvoltage limit, an ov condition might temporarily be detected resulting in undesirable behavior and possible damage to the switcher. if vout_ov_fault_response is set to ov_pulldown or 0 x00, the gpio pin will not assert if vout_ov_fault is propagated. the ltc3883 will pull the tg low and assert the bg bit as soon as the overvoltage condition is detected. this command has two data bytes and is formatted in linear_16u format. vout_ov_warn_limit the vout_ov_warn_limit command sets the value of the output voltage measured at the sense pins, in volts, which causes an output voltage high warning. the mfr_vout_peak value will be used to determine if this limit has been exceeded. in response to the vout_ov_warn_limit being exceeded, the device: ? sets the none_of_the_above bit in the status_byte ? sets the vout bit in the status_word ? sets the vout overvoltage warning bit in the status_vout command ? notifies the host by asserting alert pin this condition is detected by the adc so the response time may be up to 120ms. this command has two data bytes and is formatted in linear_16u format. vout_margin_high the vout_margin_high command loads the unit with the voltage to which the output is to be changed, in volts, when the operation command is set to margin high. the value must be greater than vout_command. this command will not be acted on during ton_ rise and toff _ fall output seq uencing. the vou t_ transition _ rate will be used if this command is modified while the output is active and in a steady-state condition. this command has two data bytes and is formatted in linear_16u format.
ltc3883/LTC3883-1 73 3883f pmb us c omman d de t ails vout_command the vout_command consists of two bytes and is used to set the output voltage, in volts. this command will not be acted on during ton _ rise and toff _ fall output sequencing. the vout _ transition _ rate will be used if this command is modified while the output is active and in a steady-state condition. this command has two data bytes and is formatted in linear_16u format. vout_margin_low the vout_margin_low command loads the unit with the voltage to which the output is to be changed, in volts, when the operation command is set to margin low. the value must be less than vout_command. this command will not be acted on during ton_ rise and toff _ fall output sequencing. the vout _ transition _ rate will be used if this command is modified while the output is active and in a steady-state condition. this command has two data bytes and is formatted in linear_16u format. vout_uv_warn_limit the vout_uv_ warn_limit command reads the value of the output voltage measured at the sense pins, in volts, which causes an output voltage low warning. in response to the vout _uv_warn_limit being exceeded, the device: ? sets the none_of_the_above bit in the status_by te ? sets the vout bit in the status_word ? sets the vout undervoltage warning bit in the status_vout command ? notifies the host by asserting alert pin this condition is detected by the adc so the response time may be up to 120ms. this command has two data bytes and is formatted in linear_16u format. vout_uv_fault_limit the vout_uv_fault_limit command reads the value of the output voltage measured at the sense pins, in volts, which causes an output undervoltage fault. this command has two data bytes and is formatted in linear_16u format. power_good_on the power_good_on command sets the output voltage at which the power_ good# status bit in the status_ word command should be de-asserted. power_good_on is detected with an a/d read resulting in latency of up to 120 ms. the power_good_on value must be set higher than the power_good_off value. this command has two data bytes and is formatted in linear_16u format. power_good_off the power _ good _ off command sets the output vo ltage at which the power _ good# status bit in the status _ word command should be asserted. power_good_off is detected with an a/d read resulting in latency of up to 120ms. the power_good_off value must be set lower than the power_good_on value.
ltc3883/LTC3883-1 74 3883f pmb us c omman d de t ails at initial power up the state of the pgood pin will be high regardless of vout. if the proper state of low at power-up is required, place a schottky diode between run and pgood. the anode must be tied to pgood and the cathode to run. the power_ good# status bit is masked from initiating an alert . the power_ good# status bit in the status_ word command is always reflective of vout with respect to the power_good threshold regardless of the run state. the pgood pin state is controlled by the power_good# status bit and is qualified by the run state. this command has two data bytes and is formatted in linear_16u format. mfr_vout_max the mfr_vout_max command is the maximum output voltage in volts the part can produce. if the output voltage is set to high range ( bit 6 of mfr_pwm_config_ltc3883 set to a 0) mfr_vout_max is 5.5 v. if the output voltage is set to low range (bit 6 of mfr_pwm_config_ltc3883 set to a 1) the mfr_vout_max is 2.75 v. entering a vout_command value greater than this will result in a cml fault and the output voltage setting will be clamped to the maximum level. this will also result in bit 3 vout_max_warning in the status_vout command being set. this read only command has 2 data bytes and is formatted in linear_16u format. c urrent output current calibration command name cmd code description type d ata format units nvm default value iout_cal_gain 0x38 the ratio of the voltage at the current sense pins to the sensed current. for devices using a fixed current sense resistor, it is the resistance value in m. r/w word l11 m y 1.8 0xbb9a mfr_iout_cal_gain_tc 0xf6 temperature coefficient of the current sensing element. r/w word cf y 3900 0x0f3c mfr_t_self_heat 0xb8 reports the calculated self heat value attributed to the inductor. r word l11 c na mfr_iout_cal_gain_ tau_inv 0xb9 coefficient used to emulate thermal time constant. r/w word l11 s C1 y 0.0 0x8000 mfr_iout_cal_gain_ theta 0xba used to calculate the instance inductor self heating effect. r/w word l11 c/w y 0.0 0x8000 iout_cal_gain the iout_cal_gain command is used to set the resistance value of the current sense resistor in milliohms . (see also mfr_iout_cal_gain_tc). this command has two data bytes and is formatted in linear_5s_11s format. mfr_iout_cal_gain_tc the mfr_ iout_ cal_ gain_ tc command allows the user to program the temperature coefficient of the iout_ cal_ gain sense resistor or inductor dcr in ppm/c. this command has two data bytes and is formatted in 16-bit 2 s complement integer ppm. n = C32768 to 32767 ? 10 C6 . nominal temperature is 27c. the iout_cal_gain is multiplied by: [1.0 + mfr_iout_cal_gain_tc ? ( read_temperature_1 - 27)]. dcr sensing will have a typical value of 3900.
ltc3883/LTC3883-1 75 3883f pmb us c omman d de t ails the iout_cal_gain and mfr_iout_cal_gain_tc impact all current parameters including: read_iout, mfr_ read_iin_chan, iout_oc_fault_limit and iout_oc_warn_limit. mfr_t_self_heat, mfr_iout_cal_gain_tau_inv and mfr_iout_cal_gain_theta the ltc3883 uses an innovative ( patent pending) algorithm to dynamically model the temperature rise from the external temperature sensor to the inductor core. this temperature rise is called mfr_t_self_heat and is used to calculate the final temperature correction required by iout_cal_gain. the temperature rise is a function of the power dissipated in the inductor dcr, the thermal resistance from the inductor core to the remote temperature sensor and the thermal time constant of the inductor to board system. the algorithm simplifies the placement requirements for the external temperature sensor and compensates for the significant steady state and transient temperature error from the inductor core to the primary inductor heat sink. the best way to understand the self heating effect inside the inductor is to model the system using the circuit analogy of figure 21 . the 1 st order differential equation for the above model may be approximated by the following difference equation: p i C t i / is = c ?t i /?t (eq1) (when t s = 0) from which: ?t i = ?t (p i is C t i )/( is c ) (eq2) or ?t i = (p i is C t i ) ? inv (eq3) where inv = ?t/( is c ) (eq4) and ?t is the sample period of the external temperature adc. the ltc3883 implements the self heating algorithm using eq3 and eq4 where: ?t i = ? mfr_t_self_heat p i = read_iout ? (v isensep C v isensem ) t s = read_temperature_1 t i = mfr_t_self_heat + t s ?t = 1s inv = mfr_iout_cal_gain_tau_inv is = mfr_iout_cal_gain_theta initially self heat is set to zero. after each temperature measurement self heat is updated to be the previous value of self heat incremented or decremented by ? mfr_t_self_heat. the actual value of c is not required. the important quantity is the thermal time constant inv = ( is c ). for example, if an inductor has a thermal time constant thermal = 5 seconds then: mfr_iout_cal_gain_tau_inv = ?t / thermal = 1/5 = 0.2 refer to the application section for more information on calibrating is and inv .
ltc3883/LTC3883-1 76 3883f pmb us c omman d de t ails if the external temperature sense network fails to detect a read_temperature_1 reading of C50 c to 150 c, the variable t s in the self-heating algorithm will be set to a fixed value of C50 c. see read_temperature_1 for more information. mfr_t_self_heat is a read-only command that has two data bytes and is formatted in linear_5_11s format. mfr_iout_cal_gain_tau_inv has two data bytes and is formatted in linear_5_11 format. mfr_iout_cal_gain_theta has two data bytes and is formatted in linear_5_11 format. mfr_t_self_heat data content bit(s) symbol operation b[15:0] mfr_t_self_heat values are limited to the range 0c to 50c. mfr_iout_cal_gain_theta data content bit(s) symbol operation b[15:0] mfr_iout_cal_gain_theta values 0 set mfr_t_self_heat to zero. mfr_iout_cal_gain_tau_inv data content bit(s) symbol operation b[15:0] mfr_iout_cal_gain_tau_inv values 0 set mfr_t_self_heat to zero. values 1 set mfr_t_self_heat to mfr_iout_cal_gain_theta ? read_iout ? (v isensep C v isensem ). output current command name cmd code description type d ata format units nvm default value iout_oc_fault_limit 0x46 output overcurrent fault limit. r/w word l11 a y 29.75 0xdbb8 iout_oc_warn_limit 0x4a output overcurrent warning limit. r/w word l11 a y 20.0 0xda80 iout_oc_fault_limit the iout_oc_fault_limit command sets the value of the peak output current limit, in amperes. when the controller is in current limit, the overcurrent detector will indicate an overcurrent fault condition. the programmed overcurrent fault limit value is rounded up to the nearest one of the following set of discrete values: 25mv/iout_cal_gain low range (1.5x nominal loop gain) mfr_pwm_mode_ lt c 3883 [7]=0 28.6mv/iout_cal_gain 32.1mv/iout_cal_gain 35.7mv/iout_cal_gain 39.3mv/iout_cal_gain 42.9mv/iout_cal_gain 46.4mv/iout_cal_gain 50mv/iout_cal_gain
ltc3883/LTC3883-1 77 3883f pmb us c omman d de t ails 37.5mv/iout_cal_gain high range (nominal loop gain) mfr_pwm_mode_ lt c 3883 [7]=1 42.9mv/iout_cal_gain 48.2mv/iout_cal_gain 53.6mv/iout_cal_gain 58.9mv/iout_cal_gain 64.3mv/iout_cal_gain 69.6mv/iout_cal_gain 75mv/iout_cal_gain note: this is the peak of the current waveform. the read_iout command returns the average current. the peak output current limits are adjusted with temperature based on the mfr_iout_cal_gain_tc using the equation: iout_oc_fault_limit = iout_cal_gain ? (1 + mfr_iout_cal_gain_tc ? (read_temperture_1-27.0)). the ltpowerplay gui automatically convert the voltages to currents. the i out range is set with bit 7 of the mfr_pwm_mode_ lt c 3883 command. the iout_oc_fault_limit is ignored during ton_rise and toff_fall. this command has two data bytes and is formatted in linear_5s_11s format. iout_oc_warn_limit this command sets the value of the output current that causes an output overcurrent warning in amperes. the read_iout value will be used to determine if this limit has been exceeded. in response to the iout_oc_warn_limit being exceeded, the device: ? sets the none_of_the_above bit in the status_byte ? sets the iout bit in the status_word ? sets the iout overcurrent warning bit in the status_iout command, and ? notifies the host by asserting alert pin this condition is detected by the adc so the response time may be up to 120ms. the iout_oc_fault_limit is ignored during ton_rise and toff_fall. this command has two data bytes and is formatted in linear_5s_11s format input current calibration command name cmd code description type d ata format units nvm default value mfr_iin_cal_gain 0xe8 the resistance value of the input current sense element in m. r/w word l11 m y 5.000 0xca80 mfr_iin_cal_gain the iout_cal_gain command is used to set the resistance value of the input current sense resistor in milliohms. (see also read_iin). this command has two data bytes and is formatted in linear_5s_11s format.
ltc3883/LTC3883-1 78 3883f pmb us c omman d de t ails input current command name cmd code description type d ata format units nvm default value iin_oc_warn_limit 0x5d input overcurrent warning limit. r/w word l11 a y 10.0 0xd280 iin_oc_warn_limit the iin_oc_warn_limit command sets the value of the input current, in amperes, that causes a warning indicating the input current is high. the read_iin value will be used to determine if this limit has been exceeded. in response to the iin_oc_warn_limit being exceeded, the device: ? sets the other bit in the status_byte ? sets the input bit in the upper byte of the status_word ? sets the iin overcurrent warning bit in the status_input command, and ? notifies the host by asserting alert pin this condition is detected by the adc so the response time may be up to 120ms. this command has two data bytes and is formatted in linear_5s_11s format. t empera ture external t emperature calibration command name cmd code description type d ata format units nvm default value mfr_temp_1_gain 0xf8 sets the slope of the external temperature sensor. r/w word cf y 1.0 0x4000 mfr_temp_1_offset 0xf9 sets the offset of the external temperature sensor with respect to C273.1c. r/w word l11 c y 0.0 0x8000 mfr_temp_1_gain the mfr_temp_1_gain command will modify the slope of the external temperature sensor to account for non-idealities in the element and errors associated with the remote sensing of the temperature in the inductor. this command has two data bytes and is formatted in 16- bit 2 s complement integer. n = 8192 to 32767. the effective adjustment is n ? 2 C14 . the nominal value is 1. mfr_temp_1_offset the mfr_temp_1_offset command will modify the offset of the external temperature sensor to account for non- idealities in the element and errors associated with the remote sensing of the temperature in the inductor. this command has two data bytes and is formatted in linear_5s_11s format. the part starts the calculation with a value of C273.15 so the default adjustment value is zero.
ltc3883/LTC3883-1 79 3883f pmb us c omman d de t ails external temperature limits command name cmd code description type d ata format units nvm default value ot_fault_limit 0x4f external overtemperature fault limit. r/w word l11 c y 100.0 0xeb20 ot_warn_limit 0x51 external overtemperature warning limit. r/w word l11 c y 85.0 0xeaa8 ut_fault_limit 0x53 external undertemperature fault limit. r/w word l11 c y C40.0 0xe580 ot_fault_limit the ot_fault_limit command sets the value of the external sense temperature, in degrees celsius, which causes an overtemperature fault. the read_temperature_1 value will be used to determine if this limit has been exceeded. this condition is detected by the adc so the response time may be up to 120ms. this command has two data bytes and is formatted in linear_5s_11s format. ot_warn_limit the ot_warn_limit command sets the value of the external sense temperature, in degrees celsius, which causes an overtemperature warning. the read_temperature_1 value will be used to determine if this limit has been exceeded. in response to the ot_warn_limit being exceeded, the device: ? sets the temperature bit in the status_byte ? sets the overtemperature warning bit in the status_temperature command, and ? notifies the host by asserting alert pin. this condition is detected by the adc so the response time may be up to 120ms. this command has two data bytes and is formatted in linear_5s_11s format. ut_fault_limit the ut_fault_limit command sets the value of the external sense temperature, in degrees celsius, which causes an undertemperature fault. the read_temperature_1 value will be used to determine if this limit has been exceeded. note: if the temp sensors are not installed, the ut_fault_limit can be set to C275 c and ut_fault_limit response set to ignore to avoid alert being asserted. this condition is detected by the adc so the response time may be up to 120ms. this command has two data bytes and is formatted in linear_5s_11s format.
ltc3883/LTC3883-1 80 3883f pmb us c omman d de t ails t iming timingon sequence/ramp command name cmd code description type d ata format units nvm default value ton_delay 0x60 time from run and/or operation on to output rail turn-on. r/w word l11 ms y 0.0 0x8000 ton_rise 0x61 time from when the output starts to rise until the output voltage reaches the vout commanded value. r/w word l11 ms y 8.0 0xd200 ton_max_fault_limit 0x62 maximum time from v out_en on for vout to cross the vout_uv_fault_limit. r/w word l11 ms y 10.0 0xd280 vout_transition_rate 0x27 rate the output changes when vout commanded to a new value. r/w word l11 v/ms y 0.25 0xaa00 ton_delay the ton_delay command sets the time, in milliseconds, from when a start condition is received until the output voltage starts to rise. values from 0 ms to 83 seconds are valid. the ton_delay will have a typical delay of 270s with an uncertainty of 50s. this command has two data bytes and is formatted in linear_5s_11s format. ton_rise the ton_rise command sets the time, in milliseconds, from the time the output starts to rise to the time the output enters the regulation band. values from 0 to 1.3 seconds are valid . the part will be in discontinuous mode during ton_rise events. if ton_rise is less than 0.25 ms, the ltc3883 digital slope will be bypassed. the output voltage transition will be controlled by the analog performance of the pwm switcher. the number of steps in ton_rise is equal to ton_rise (in ms)/0.1ms with an uncertainty of 0.1ms. this command has two data bytes and is formatted in linear_5s_11s format. ton_max_fault_limit the ton_max_fault_limit command sets the value, in milliseconds, on how long the unit can attempt to power up the output without reaching the output undervoltage fault limit. a data value of 0 ms means that there is no limit and that the unit can attempt to bring up the output voltage indefinitely. the maximum limit is 83 seconds. this command has two data bytes and is formatted in linear_5s_11s format. vout_transition_rate when a pmbus device receives either a vout_command or operation ( margin high, margin low) that causes the output voltage to change this command set the rate in v/ms at which the output voltage changes. this commanded rate of change does not apply when the unit is commanded on or off. the maximum allowed slope is 4v/ms.
ltc3883/LTC3883-1 81 3883f pmb us c omman d de t ails this command has two data bytes and is formatted in linear_5s_11s format. timingoff sequence/ramp command name cmd code description type d ata format units nvm default value toff_delay 0x64 time from run and/or operation off to the start of toff_fall ramp. r/w word l11 ms y 0.0 0x8000 toff_fall 0x65 time from when the output starts to fall until the output reaches zero volts. r/w word l11 ms y 8.0 0xd200 toff_max_warn_limit 0x66 maximum allowed time, after toff_fall completed, for the unit to decay below 12.5%. r/w word l11 ms y 150 0xf258 toff_delay the toff_delay command sets the time, in milliseconds, from when a stop condition is received until the output voltage starts to fall. values from 0 to 83 seconds are valid. the ton_delay will have a typical delay of 270 s with an uncertainty of 50s. this command is excluded from fault events. this command has two data bytes and is formatted in linear_5s_11s format. toff_fall the toff_fall command sets the time, in milliseconds, from the end of the turn-off delay time until the output volt- age is commanded to zero. it is the ramp time of the v out dac. when the v out dac is zero, the part will three-state. the part will maintain the mode of operation programmed. for defined toff_fall times, the user should set the part to continuous conduction mode. loading the max value indicates the part will ramp down at the slowest possible rate. the minimum supported fall time is 0.25 ms. a value less than 0.25 ms will result in a 0.25 ms ramp. the maximum fall time is 1.3 seconds. the number of steps in toff_fall is equal to toff_fall ( in ms)/0.1ms with an uncertainty of 0.1ms. in discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by the output capacitance and load current. this command has two data bytes and is formatted in linear_5s_11s format. toff_max_warn_limit the toff_max_warn_limit command sets the value, in milliseconds, on how long the unit can attempt to turn off the output until a warning is asserted. the output is considered off when the v out voltage is less than 12.5% of the programmed vout_command value. the calculation begins after toff_fall is complete. a data value of 0 ms means that there is no limit and that the unit can attempt to turn off the output voltage indefinitely. other than 0, values from 120ms to 524 seconds are valid. this command has two data bytes and is formatted in linear_5s_11s format. precondition for restart command name cmd code description type d ata format units nvm default value mfr_restart_ delay 0xdc minimum time the run pin is held low by the ltc3883. r/w word l11 ms y 500 0xfbe8
ltc3883/LTC3883-1 82 3883f pmb us c omman d de t ails mfr_restart_delay this command specifies the minimum run off time in milliseconds. this device will pull the run pin low for this length of time once a falling edge of run has been detected. the minimum recommended value is 136ms. note: the restart delay is different than the retry delay. the restart delay pulls run low for the specified time, after which a standard start-up sequence is initiated. the minimum restart delay should be equal to toff_delay + toff_ fall + 136 ms. valid values are from 136 ms to 65.52 seconds in 16 ms increments. to assure a minimum off time, set the mfr_restart_delay 16 ms longer than the desired time. the output rail can be off longer than the mfr_ restart_delay after the run pin is pulled high if the output decay bit 0 is enabled in mfr_chan_config_ lt c 3883 and the output takes a long time to decay below 12.5% of the programmed value. this command has two data bytes and is formatted in linear_5s_11s format. f ault r esponse fault responses all faults command name cmd code description type d ata format units nvm default value mfr_retry_ delay 0xdb retry interval during fault retry mode. r/w word l11 ms y 350 0xfabc mfr_retry_delay this command sets the time in milliseconds between retries if the fault response is to retry the controller at specified intervals. this command value is used for all fault responses that require retry. the retry time starts once the fault has been detected by the offending channel. valid values are from 120ms to 83.88 seconds in 10s increments. note: the retry delay time is determined by the longer of the mfr_retry_delay command or the time required for the regulated output to decay below 12.5% of the programmed value. if the natural decay time of the output is too long, it is possible to remove the voltage requirement of the mfr_retry_delay command by asserting bit 0 of mfr_chan_config_ lt c 3883. this command has two data bytes and is formatted in linear_5s_11s format. fault responses input voltage command name cmd code description type d ata format units nvm default value vin_ov_fault_response 0x56 action to be taken by the device when an input supply overvoltage fault is detected. r/w byte reg y 0x80 vin_ov_fault_response the vin_ov_fault_response command instructs the device on what action to take in response to an input over- voltage fault. the data byte is in the format given in table 9. the device also: ? sets the none_of_the_above bit in the status_byte ? set the input bit in the upper byte of the status_word
ltc3883/LTC3883-1 83 3883f pmb us c omman d de t ails ? sets the vin overvoltage fault bit in the status_input command, and ? notifies the host by asserting alert pin this command has one data byte. fault responses output voltage command name cmd code description type d ata format units nvm default value vout_ov_fault_response 0x41 action to be taken by the device when an output overvoltage fault is detected. r/w byte reg y 0xb8 vout_uv_fault_response 0x45 action to be taken by the device when an output undervoltage fault is detected. r/w byte reg y 0xb8 ton_max_fault_ response 0x63 action to be taken by the device when a ton_max_fault event is detected. r/w byte reg y 0xb8 vout_ov_fault_response the vout_ov_fault_response command instructs the device on what action to take in response to an output overvoltage fault. the data byte is in the format given in table 5. the device also: ? sets the vout_ov bit in the status_byte ? sets the vout bit in the status_word ? sets the vout overvoltage fault bit in the status_vout command ? notifies the host by asserting alert pin the only values recognized for this command are: 0x00Cpart performs ov pull down only, or ov_pulldown. 0x80Cthe device shuts down ( disables the output) and the unit does not attempt to retry. ( pmbus, part ii, section 10.7). 0xb8Cthe device shuts down ( disables the output ) and device attempts to retry continuously, without limitation, until it is commanded off ( by the run pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down. 0x4n the device shuts down and the unit does not attempt to retry. the output remains disabled until the part is com- manded off then on or the run pin is asserted low then high or reset through the command or removal of vin. the ov fault must remain active for a period of n ? 10s, where n is a value from 0 to 7. 0x78+n the device shuts down and the unit attempts to retry continuously until either the fault condition is cleared or the part is commanded off then on or the run pin is asserted low then high or reset through the command or removal of vin. the ov fault must remain active for a period of n ? 10s, where n is a value from 0 to 7. any other value will result in a cml fault and the write will be ignored. this command has one data byte.
ltc3883/LTC3883-1 84 3883f pmb us c omman d de t ails table 5. vout_ov_fault_response data byte contents bits description value meaning 7:6 response for all values of bits [7:6], the ltc3883: ? sets the corresponding fault bit in the status commands and ? notifies the host by asserting alert pin the fault bit, once set, is cleared only when one or more of the following events occurs: ? the device receives a clear_faults command. ? the output is commanded through the run pin, the operation command, or the combined action of the run pin and operation command, to turn off and then to turn back on, or ? bias power is removed and reapplied to the ltc3883. 00 part performs ov pull down only or ov_pulldown (i.e., turns off the top mosfet and turns on lower mosfet while v out is > vout_ov_fault) 01 the pmbus device continues operation for the delay time specified by bits [2:0] and the delay time unit specified for that particular fault. if the fault condition is still present at the end of the delay time, the unit responds as programmed in the retry setting (bits [5:3]). 10 the device shuts down immediately (disables the output) and responds according to the retry setting in bits [5:3]. 11 not supported. writing this value will generate a cml fault. 5:3 retr y setting 000 the unit does not attempt to restart. the output remains disabled until the fault is cleared until the device is commanded off bias power is removed. 111 the pmbus device attempts to restart continuously, without limitation, until it is commanded off (by the run pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down without retry. note: the retry interval is set by the mfr_retry_delay command. 2:0 delay time 000-111 the delay time in 10s increments. this delay time determines how long the controller continues operating after a fault is detected. only valid for deglitched off state. vout_uv_fault_response the vout_uv_fault_response command instructs the device on what action to take in response to an output undervoltage fault. the data byte is in the format given in table 6. the device also: ? sets the none_of_the_above bit in the status_byte ? sets the vout bit in the status_word ? sets the vout undervoltage fault bit in the status_vout command ? notifies the host by asserting alert pin the uv fault and warn are masked until the following criteria are achieved: 1) the ton_max_fault_limit has been reached 2) the ton_dela y sequence has completed 3) the ton_rise sequence has completed 4) the vout_uv_fault_limit threshold has been reached 5) the iout_oc_fault_limit is not present the uv fault and warn are masked whenever the channel is not active. the uv fault and warn are masked during ton_rise and toff_f all sequencing. this command has one data byte.
ltc3883/LTC3883-1 85 3883f table 6. vout_uv_fault_response data byte contents bits description value meaning 7:6 response for all values of bits [7:6], the ltc3883: ? sets the corresponding fault bit in the status commands and ? notifies the host by asserting alert pin the fault bit, once set, is cleared only when one or more of the following events occurs: ? the device receives a clear_faults command ? the output is commanded through the run pin, the operation command, or the combined action of the run pin and operation command, to turn off and then to turn back on, or ? bias power is removed and reapplied to the ltc3883 00 the pmbus device continues operation without interruption. (ignores the fault functionally) 01 the pmbus device continues operation for the delay time specified by bits [2:0] and the delay time unit specified for that particular fault. if the fault condition is still present at the end of the delay time, the unit responds as programmed in the retry setting (bits [5:3]). 10 the device shuts down (disables the output) and responds according to the retry setting in bits [5:3]. 11 not supported. writing this value will generate a cml fault. 5:3 retry setting 000 the unit does not attempt to restart. the output remains disabled until the fault is cleared until the device is commanded off bias power is removed. 111 the pmbus device attempts to restart continuously, without limitation, until it is commanded off (by the run pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down without retry. note: the retry interval is set by the mfr_retry_delay command. 2:0 delay time 000-111 the delay time in 10s increments. this delay time determines how long the controller continues operating after a fault is detected. only valid for deglitched off state. ton_max_fault_response the ton_max_fault_response command instructs the device on what action to take in response to a ton_max fault. the data byte is in the format given in table 9. the device also: ? sets the none_of_the_above bit in the status_byte ? sets the vout bit in the status_word ? sets the ton_max_fault bit in the status_vout command, and ? notifies the host by asserting alert pin a value of 0 disables the ton_max_fault_response. it is not recommended to use 0. this command has one data byte. fault responses output current command name cmd code description type d ata format units nvm default value iout_oc_fault_response 0x47 action to be taken by the device when an output overcurrent fault is detected. r/w byte reg y 0x00 pmb us c omman d de t ails
ltc3883/LTC3883-1 86 3883f iout_oc_fault_response the iout_oc_fault_response command instructs the device on what action to take in response to an output overcurrent fault. the data byte is in the format given in table 7. the device also: ? sets the none_of_the_above bit in the status_byte ? sets the iout_oc bit in the status_byte ? sets the iout bit in the status_word ? sets the iout overcurrent fault bit in the status_iout command, and ? notifies the host by asserting alert pin this command has one data byte. table 7. iout_oc_fault_response data byte contents bits description value meaning 7:6 response for all values of bits [7:6], the ltc3883: ? sets the corresponding fault bit in the status commands and ? notifies the host by asserting alert pin the fault bit, once set, is cleared only when one or more of the following events occurs: ? the device receives a clear_faults command ? the output is commanded through the run pin, the operation command, or the combined action of the run pin and operation command, to turn off and then to turn back on, or ? bias power is removed and reapplied to the ltc3883. 00 the ltc3883 continues to operate indefinitely while maintaining the output current at the value set by iout_oc_fault_limit without regard to the output voltage (known as constant- current or brick-wall limiting). 01 not supported. 10 the ltc3883 continues to operate, maintaining the output current at the value set by iout_oc_fault_limit without regard to the output voltage, for the delay time set by bits [2:0]. if the device is still operating in current limit at the end of the delay time, the device responds as programmed by the retry setting in bits [5:3]. 11 the ltc3883 shuts down immediately and responds as programmed by the retr y setting in bits [5:3]. 5:3 retry setting 000 the unit does not attempt to restart. the output remains disabled until the fault is cleared by cycling the run pin or removing bias power. 111 the device attempts to restart continuously, without limitation, until it is commanded off (by the run pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down. note: the retry interval is set by the mfr_retry_delay command. 2:0 delay time 000-111 the number of delay time units in 16ms increments. this delay time is used to determine the amount of time a unit is to continue operating after a fault is detected before shutting down. only valid for deglitched off response. fault responses ic temperature command name cmd code description type d ata format units nvm default value mfr_ot_fault_ response 0xd6 action to be taken by the device when an internal overtemperature fault is detected r byte reg 0xc0 pmb us c omman d de t ails
ltc3883/LTC3883-1 87 3883f mfr_ot_fault_response the mfr_ot_fault_response command byte instructs the device on what action to take in response to an internal overtemperature fault. the data byte is in the format given in table 8. the ltc3883 also: ? sets the none_of_the_above bit in the status_byte ? sets the mfr bit in the status_word, and ? sets the overtemperature fault bit in the status_mfr_specific command ? notifies the host by asserting alert pin this command has one data byte. table 8. data byte contents mfr_ot_fault_response bits description value meaning 7:6 response for all values of bits [7:6], the ltc3883: ? sets the corresponding fault bit in the status commands and ? notifies the host by asserting alert pin the fault bit, once set, is cleared only when one or more of the following events occurs: ? the device receives a clear_faults command ? the output is commanded through the run pin, the operation command, or the combined action of the run pin and operation command, to turn off and then to turn back on, or ? bias power is removed and reapplied to the ltc3883 00 not supported. writing this value will generate a cml fault. 01 not supported. writing this value will generate a cml fault 10 the device shuts down immediately (disables the output) and responds according to the retry setting in bits [5:3]. 11 the devices output is disabled while the fault is present. operation resumes and the output is enabled when the fault condition no longer exists. 5:3 retry setting 000 the unit does not attempt to restart. the output remains disabled until the fault is cleared. 001-111 not supported. writing this value will generate cml fault. 2:0 delay time xxx not supported. value ignored fault responses external temperature command name cmd code description type d ata format units nvm default value ot_fault_ response 0x50 action to be taken by the device when an external overtemperature fault is detected, r/w byte reg y 0xb8 ut_fault_ response 0x54 action to be taken by the device when an external undertemperature fault is detected. r/w byte reg y 0xb8 ot_fault_response the ot_fault_response command instructs the device on what action to take in response to an external overtem- perature fault on the external temp sensors. the data byte is in the format given in table 9. the device also: ? sets the temperature bit in the status_byte ? sets the overtemperature fault bit in the status_temperature command, and ? notifies the host by asserting alert pin pmb us c omman d de t ails
ltc3883/LTC3883-1 88 3883f this condition is detected by the adc so the response time may be up to 120ms. this command has one data byte. ut_fault_response the ut_fault_response command instructs the device on what action to take in response to an external under- temperature fault on the external temp sensors. the data byte is in the format given in table 9. the device also: ? sets the temperature bit in the status_byte ? sets the undertemperature fault bit in the status_temperature command, and ? notifies the host by asserting alert pin this condition is detected by the adc so the response time may be up to 120ms. this command has one data byte. table 9. data byte contents: ton_max_fault_response, vin_ov_fault_response, ot_fault_response, ut_fault_response bits description value meaning 7:6 response for all values of bits [7:6], the ltc3883: ? sets the corresponding fault bit in the status commands, and ? notifies the host by asserting alert pin the fault bit, once set, is cleared only when one or more of the following events occurs: ? the device receives a clear_faults command ? the output is commanded through the run pin, the operation command, or the combined action of the run pin and operation command, to turn off and then to turn back on, or ? bias power is removed and reapplied to the ltc3883 00 the pmbus device continues operation without interruption. 01 not supported. writing this value will generate a cml fault. 10 the device shuts down immediately (disables the output) and responds according to the retry setting in bits [5:3]. 11 not supported. writing this value will generate a cml fault. 5:3 retry setting 000 the unit does not attempt to restart. the output remains disabled until the fault is cleared until the device is commanded off bias power is removed. 111 the pmbus device attempts to restart continuously, without limitation, until it is commanded off ( by the run pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down without retry. note: the retry interval is set by the mfr_retry_dela y command. 2:0 delay time xxx not supported. values ignored f ault s haring fault sharing propagation command name cmd code description type d ata format units nvm default value mfr_gpio_ propagate_ lt c 3883 0xd2 configuration that determines which faults are propagated to the gpio pins. r/w word reg y 0x2993 pmb us c omman d de t ails
ltc3883/LTC3883-1 89 3883f mfr_gpio_propagate_ ltc 3883 the mfr_gpio_propagate_ lt c 3883 command enables the events that can cause the gpio pin to assert low. the command is formatted as shown in table 10. faults can only be propagated to the gpio pin if they are programmed to respond to faults. this command has two data bytes. table 10: gpio propagate configuration the gpio pin is designed to provide electrical notification of selected events to the user. bit(s) symbol operation b[15] vout disabled while not decayed. this status bit is used in a polyphase configuration when bit 0 of the mfr_chan_config_ lt c 3883 is a zero. if the pwm is turned off, by toggling the run pin or commanding the part off, and then the run is reasserted or the part is commanded back on before the output has decayed, vout will not restart until the 12.5% decay is honored. the gpio pin is asserted during this condition if bit 15 is asserted. b[14] mfr_gpio_propagate_short_cmd_cycle 0: no action 1: this status bit asserts low if commanded off then on before the output has sequenced off. re-asserts high after sequence off. b[13] mfr_gpio_propagate_ton_max_fault 0: no action if a ton_max_fault fault is asserted 1: gpio will be asserted low if a ton_max_fault fault is asserted b[12] mfr_gpio_propagate_vout_uvuf deglitched vout_uv_fault_limit comparator output with a 250s minimum pulse width filter. if this status bit is asserted, gpio is low anytime vout is below the uv threshold. if the gpio_ fault_response is not set to ignore, the part will latch off and never be able to start. b [11] mfr_gpio_propagate_int_ot 0: no action if the mfr_ot_fault_limit fault is asserted 1: output will be asserted low if the mfr_ot_fault_limit fault is asserted b[10] reserved must be set to 0 b[9] mfr_pwrgd_en (note 1) 0: no action if power_good is not true 1: gpio will be asserted low if power_good is not true if this status bit is asserted, the gpio_fault_response must be ignore. if the gpio_fault_ response is not set to ignore, the part will latch off and never be able to start. b[8] mfr_gpio_propagate_ut 0: no action if the ut_fault_limit fault is asserted 1: gpio will be asserted low if the ut_fault_limit fault is asserted b[7] mfr_gpio_propagate_ot 0: no action if the ot_fault_limit fault is asserted 1: gpio will be asserted low if the ot_fault_limit fault is asserted b[6] reserved b[5] reserved b[4] mfr_gpio_propagate_input_ov 0: no action if the vin_ov_fault_limit fault is asserted 1: gpio will be asserted low if the vin_ov_fault_limit fault is asserted b[3] reserved b[2] mfr_gpio_propagate_iout_oc 0: no action if the iout_oc_fault_limit fault is asserted 1: gpio will be asserted low if the iout_oc_fault_limit fault is asserted b[1] mfr_gpio_propagate_vout_uv 0: no action if the vout_uv_fault_limit fault is asserted 1: gpio will be asserted low if the vout_uv_fault_limit fault is asserted if this fault bit is asserted, gpio is low anytime vout is below the uv threshold due to a fault. a uv fault can only occur when the part is in a steady-state on condition. b[0] mfr_gpio_propagate_vout_ov 0: no action if the vout_ov_fault_limit fault is asserted 1: gpio will be asserted low if the vout_ov_fault_limit fault is asserted note 1: the pwrgd status is designed as an indicator and not to be used for power supply sequencing. pmb us c omman d de t ails
ltc3883/LTC3883-1 90 3883f fault sharing response command name cmd code description type d ata format units nvm default value mfr_gpio_response 0xd5 action to be taken by the device when the gpio pin is asserted low. r/w byte reg y 0xc0 mfr_gpio_response this command determines the controllers response to the gpio pin being pulled low by an external source. value meaning 0xc0 gpio_inhibit the ltc3883 will three-state the output in response to the gpio pin pulled low. 0x00 gpio_ignore the ltc3883 continues operation without interruption. the device also: ? sets the none_of_the_above bit in the status_byte ? sets the mfr bit in the status_word ? sets the gpiob bit in the status_mfr_specific command, and notifies the host by asserting alert pin. the alert pin pulled low can be disabled by setting bit[1] of mfr_chan_cfg_ lt c 3883. this command has one data byte. s cra tchpad command name cmd code description type d ata format units nvm default value user_data_00 0xb0 oem reserved. typically used for part serialization. r/w word reg y na user_data_01 0xb1 manufacturer reserved for ltpowerplay. r/w word reg y na user_data_02 0xb2 oem reserved. typically used for part serialization. r/w word reg y na user_data_03 0xb3 a nvm word available for the user. r/w word reg y 0x0000 user_data_04 0xb4 a nvm word available for the user. r/w word reg y 0x0000 user_data_00 through user_data_04 these commands are non-volatile memory locations for customer storage. the customer has the option to write any value to the user_data_nn at any time. however, the ltpowerplay software and contract manufacturers use some of these commands for inventory control. modifying the reserved user_data_nn commands may lead to undesirable inventory control and incompatibility with these products. these commands have 2 data bytes and are in register format. pmb us c omman d de t ails
ltc3883/LTC3883-1 91 3883f i dentification command name cmd code description type d ata format units nvm default value pmbus_revision 0x98 pmbus revision supported by this device. current revision is 1.1. r byte reg fs 0x11 capability 0x19 summary of pmbus optional communication protocols supported by this device. r byte reg 0xb0 mfr_date 0x9d date of the final test of the ic yymmdd in ascii. r string asc fs na mfr_id 0x99 the manufacturer id of the ltc3883 in ascii. r string asc lt c mfr_location 0x9c location of the final test of the ltc3883 in ascii. r string asc fs na mfr_model 0x9a manufacturer part number in ascii. r string asc ltc3883 mfr_revision 0x9b manufacturer part revision in ascii. r string asc fs na mfr_rom_crc 0xfc factory use only. r word i16 na mfr_special_id 0xe7 manufacturer code representing the ltc3883 and revision. r word reg 0x43xx mfr_trim 0xeb contact the factory, this command is used for diagnostics. r block cf na pmbus_revision the pmbus_revision command indicates the revision of the pmbus to which the device is compliant. the ltc3883 is pmbus version 1.1 compliant in both part i and part ii. this read-only command has one data byte. capability this command provides a way for a host system to determine some key capabilities of a pmbus device. the ltc3883 supports packet error checking, 400khz bus speeds, and alert pin. this read-only command has one data byte. mfr_date the mfr_date command indicates the date of final test of this ic. the mfr_date format is yymmdd where y, m and d are integer values from 0 to 9, inclusive using ascii characters. this read-only command is in block format. mfr_id the mfr_id command indicates the manufacturer id of the ltc3883 using ascii characters. this read-only command is in block format. mfr_location the mfr_location command indicates the location of final test of this ic using ascii characters. this field is limited to a maximum of three characters. this read-only command is in block format. pmb us c omman d de t ails
ltc3883/LTC3883-1 92 3883f mfr_model the mfr_model command indicates the manufacturers part number of the ltc3883 using ascii characters. this read-only command is in block format. mfr_revision the mfr_revision command indicates the manufacturers revision number of the ltc3883 using ascii characters. this field is limited to a maximum of five characters. this read-only command is in block format. mfr_rom_crc this device performs a 16- bit ccitt crc calculation of the internal rom upon power-up or reset of the device. the result of this operation may be reviewed by the user. a non-zero value should not be construed as a rom failure. the device manufacturer reserves the right to make modifications to the rom. this read-only command has two data bytes. mfr_special_id the 16- bit word representing the part name and revision. 0 x43 denotes the part is an ltc3883, xx is adjustable by the manufacturer. this read-only command has two data bytes. mfr_trim the mfr_trim block read command provides access to factory trim bits. the meaning of these bits is confidential and proprietary to lt c . this will provide a means of field examination of an individual parts trim contents . this block command length fixed of five bytes. this read-only command is in block format. f ault w arning and s t atus command name cmd code description type format units nvm default value clear_faults 0x03 clear any fault bits that have been set. send byte na mfr_clear_peaks 0xe3 clears all peak values. send byte na status_byte 0x78 one byte summary of the units fault condition. r/w byte reg na status_word 0x79 tw o byte summary of the units fault condition. r/w word reg na status_vout 0x7a output voltage fault and warning status. r/w byte reg na status_iout 0x7b output current fault and warning status. r/w byte reg na status_input 0x7c input supply fault and warning status. r/w byte reg na status_ temperature 0x7d external temperature fault and warning status for read_temerature_1. r/w byte reg na status_cml 0x7e communication and memory fault and warning status. r/w byte reg na status_mfr_ specific 0x80 manufacturer specific fault and state information. r/w byte reg na mfr_pads 0xe5 digital status of the i/o pads. r word reg na mfr_common 0xef manufacturer status bits that are common across multiple lt c chips. r byte reg na pmb us c omman d de t ails
ltc3883/LTC3883-1 93 3883f clear_faults the clear_faults command is used to clear any fault bits that have been set. this command clears all bits in all status commands simultaneously. at the same time, the device negates ( clears, releases) its alert pin signal output if the device is asserting the alert pin signal. the clear_faults does not cause a unit that has latched off for a fault condition to restart. units that have shut down for a fault condition are restarted when: ? the output is commanded through the run pin, the operation command, or the combined action of the run pin and operation command, to turn off and then to turn back on, or ? mfr_reset command is issued. ? bias power is removed and reapplied to the integrated cir cuit if the fault is still present when the bit is cleared, the fault bit will remain set and the host notified by asserting the alert pin pin low. this write-only command has no data bytes. mfr_clear_peaks the mfr_clear_peaks command clears the mfr_*_peak data values. the mfr_reset command will initiate this command. this write-only command has no data bytes. status_byte the status_byte command returns one byte of information with a summary of the most critical faults. this is the lower byte of the status word. the following status bits can be cleared by writing a 1 to their position in the status_by te command: [7] busy this permits the user to clear status by means other than using the clear_faults command. this is also the only bit of this command that can initiate an alert event. [6] bit 6 of this command will be set whenever the pwm is turned off. setting this bit does not assert alert. this command has one data byte. status_word the status_word command returns two bytes of information with a summary of the units fault condition. the following status bits can be cleared by writing a 1 to their position in the status_word command: [8] unknown [7] busy this permits the user to clear status by means other than using the clear_faults command. these are also the only bits of this command that can initiate an alert event. [6] bit 6 of this command will be set whenever the output is turned off. [11] bit 11 of this command will be set whenever the output voltage is below the power_good_off threshold. pmb us c omman d de t ails
ltc3883/LTC3883-1 94 3883f if any of the bits in the upper byte are set, none_of_the_above is asserted. [14] bit 14 of this command will be set by an iout_oc warning or iout_oc fault condition. this command has two data bytes. status_vout the status_vout commands returns one byte with status information on v out . bit 0 of this command is undefined and reserved in the ltc3883. the user is permitted to write a 1 to any bit in this command to clear a specific fault. this permits the user to clear status by means other than using the clear_faults command. any supported fault bit in this command will initiate an alert event. this command has one data byte. status_iout the status_iout commands returns one byte with status information on i out . only bits 7, 6, and 5 are supported in the ltc3883. the user is permitted to write a 1 to any bit in this command to clear a specific fault. this permits the user to clear status by means other than using the clear_faults command. any supported fault bit in this command will initiate an alert event. this command has one data byte. status_input the status_input commands returns one byte with status information on v in . only bits 7, 5 and 1 are supported in the ltc 3883 . the user is permitted to write a 1 to any bit in this command to clear a specific fault. this permits the user to clear status by means other than using the clear_faults command. any supported fault bit in this command will initiate an alert event. bit 3 of this command is not latched and will not generate an alert even if it is set. this command has one data byte. status_temperature the status_temperature commands returns one byte with status information on temperature. this command is related to the respective read_temperature_1 value. only bits 7, 6 and 4 are supported in the ltc3883. the user is permitted to write a 1 to any bit in this command to clear a specific fault. this permits the user to clear status by means other than using the clear_faults command. any supported fault bit in this command will initiate an alert event. this command has one data byte. pmb us c omman d de t ails
ltc3883/LTC3883-1 95 3883f pmb us c omman d de t ails status_cml the status_cml commands returns one byte with the status information on received commands and system memory/logic. bit 2 of this command is not supported in the ltc3883. if either bit 3 or bit 4 of this command is set, a serious and significant internal error has been detected. continued operation of the part is not recommended if these bits are continuously set. the user is permitted to write a 1 to any bit in this command to clear a specific fault. this permits the user to clear status by means other than using the clear_faults command. any supported fault bit in this command will initiate an alert event. this command has one data byte. status_mfr_specific the status_mfr_specific commands returns one byte with the manufacturer specific status information. the format for this byte is: bit meaning 7 internal temperature fault limit exceeded. 6 internal temperature warn limit exceeded. 5 factory trim area nvm crc fault. 4 pll is unlocked 3 fault log present 2 v dd33 uv or ov fault 0 gpio pin asserted low by external device if any of these bits are set, the mfr bit in the status_word will be set. the user is permitted to write a 1 to any bit in this command to clear a specific fault. this permits the user to clear status by means other than using the clear_faults command. exception: the fault log present bit can only be cleared by issuing the mfr_fault_log_clear command. any supported fault bit in this command will initiate an alert event. this command has one data byte.
ltc3883/LTC3883-1 96 3883f pmb us c omman d de t ails mfr_pads this command provides the user a means of directly reading the digital status of the i/o pins of the device. the bit assignments of this command are as follows: bit assigned digital pin 15 v dd33 ov fault 14 v dd33 uv fault 13 reserved 12 reserved 11 adc values invalid, occurs during start-up 10 device driving alert low 9 reserved 8 power good 7 reserved 6 device driving run low 5 reserved 4 run 3 reserved 2 device driving gpio low 1 reserved 0 gpio a 1 indicates the condition is true. this read-only command has two data bytes. mfr_common the mfr_common command contains bits that are common to all lt c digital power and telemetry products. bit meaning 7 chip not driving alert low 6 busy when low 5 calculations not pending 4 output in transition when low 3 nvm initialized 2 reserved 1 share_clk timeout 0 wp pin status this read-only command has one data byte.
ltc3883/LTC3883-1 97 3883f pmb us c omman d de t ails summary of the status commands status_byte also is the lower byte of status_word 7 6 5 4 3 2 1 0 busy off vout_ov iout_oc reserved temperature cml none of the above status_word (upper byte) 7 6 5 4 3 2 1 0 vout iout/pout input mfr power_good# reserved reserved unknown status_vout 7 6 5 4 3 2 1 0 vout ov fault vout ov warning vout uv warning vout uv fault vout max warning ton max fault toff max warning reserved status_iout 7 6 5 4 3 2 1 0 iout_oc fault reserved iout_oc warning reserved reserved reserved reserved reserved status_temperature 7 6 5 4 3 2 1 0 ot fault ot warning reserved ut fault reserved reserved reserved reserved status_cml 7 6 5 4 3 2 1 0 invalid/unsupported command invalid/unsupported data packet error check failed memory fault detected processor fault detected reserved other communication fault other memory or logic fault mfr_common 7 6 5 4 3 2 1 0 chip not driving alert low chip not busy calculations not pending output not in transistion nvm initialized reserved share_clk_low wp pin status_input 7 6 5 4 3 2 1 0 vin ov fault reserved vin uv warning reserved reserved reserved iin_oc warning reserved status_mfr_specific 7 6 5 4 3 2 1 0 internal temp fault internal temp warn factory nvm crc error pll unlocked fault log present vdd33 ov/uv reserved gpio pin asserted low externally
ltc3883/LTC3883-1 98 3883f t elemetry command name cmd code description type format units nvm default value read_vin 0x88 measured input supply voltage. r word l11 v na read_iin 0x89 measured input supply current. r word l11 a na read_vout 0x8b measured output voltage. r word l16 v na read_iout 0x8c measured output current. r word l11 a na read_temperature_1 0x8d external diode junction temperature. this is the value used for all temperature related processing, including iout_cal_gain. r word l11 c na read_temperature_2 0x8e internal junction temperature. does not affect any other commands. r word l11 c na read_duty_cycle 0x94 duty cycle of the top gate control signal. r word l11 % na read_pout 0x96 calculated output power. r word l11 w na read_pin 0x97 calculated input power r word l11 w na mfr_iout_peak 0xd7 report the maximum measured value of read_iout since last mfr_clear_peaks. r word l11 a na mfr_vout_peak 0xdd maximum measured value of read_vout since last mfr_clear_peaks. r word l16 v na mfr_vin_peak 0xde maximum measured value of read_vin since last mfr_clear_peaks. r word l11 v na mfr_temperature_1_peak 0xdf maximum measured value of external temperature (read_temperature_1) since last mfr_clear _ peaks . r w ord l11 c na mfr_read_iin_chan_peak 0xe1 maximum measured value of read_iin command since last mfr_clear_peaks. r word l11 a na mfr_read_ichip 0xe4 measured current used by the ltc3883 r word l11 a na mfr_read_iin_chan 0xed calculated input supply current based upon read_iout and duty_cycle r word l11 a na mfr_temperature_2_peak 0xf4 peak internal die temperature since last mfr_clear_peaks. r word l11 c na read_vin the read_vin command returns the measured v in pin voltage, in volts added to read_ichip ? mfr_rvin. this compensates for the ir voltage drop across the v in filter element due to the supply current of the ltc3883. this read-only command has two data bytes and is formatted in linear_5s_11s format. read_vout the read_vout command returns the measured output voltage in the same format as set by the vout_mode command. this read-only command has two data bytes and is formatted in linear_16u format. read_iin the read_iin command returns the input current, in amperes, as measured across the input current sense resistor (see also mfr_iin_cal_gain). this read-only command has two data bytes and is formatted in linear_5s_11s format. pmb us c omman d de t ails
ltc3883/LTC3883-1 99 3883f read_iout the read_iout command returns the average output current in amperes. the iout value is a function of: a) the differential voltage measured across the i sense pins b) the iout_cal_gain value c) the mfr_iout_cal_gain_tc value, and d) read_temperature_1 value e) the mfr_temp_1_gain and the mfr_temp_1_offset f) the mfr_iout_cal_gain_tau_inv and mfr_iout_cal_gain_theta this read-only command has two data bytes and is formatted in linear_5s_11s format. read_temperature_1 the read_temperature_1 command returns the temperature, in degrees celsius, of the external sense element. this read-only command has two data bytes and is formatted in linear_5s_11s format. read_temperature_2 the read_temperature_2 command returns the temperature, in degrees celsius, of the internal sense element. this read-only command has two data bytes and is formatted in linear_5s_11s format. read_duty_cycle the read_duty_cycle command returns the duty cycle of controller, in percent. this read-only command has two data bytes and is formatted in linear_5s_11s format. read_pout the read_pout command is a reading of the dc/dc converter output power in watts. the pout is calculated based on the most recent correlated output voltage and current reading. this read-only command has 2 data bytes and is formatted in linear_5s_11s format. read_pin the read_pin command is a reading of the dc/dc converter input power in watts. the pin is calculated based on the most recent correlated input voltage and current reading. this read-only command has 2 data bytes and is fromatted in linear_5s_11s format. mfr_iout_peak the mfr_ iout_ peak command reports the highest current, in amperes, reported by the read_ iout measurement. this command is cleared using the mfr_clear_peaks command. this read-only command has two data bytes and is formatted in linear_5s_11s format. mfr_vout_peak the mfr_vout_peak command reports the highest voltage, in volts, reported by the read_vout measurement. this command is cleared using the mfr_clear_peaks command. this read-only command has two data bytes and is formatted in linear_16u format. pmb us c omman d de t ails
ltc3883/LTC3883-1 100 3883f mfr_vin_peak the mfr_vin_peak command reports the highest voltage, in volts, reported by the read_vin measurement. this command is cleared using the mfr_clear_peaks command. this read-only command has two data bytes and is formatted in linear_5s_11s format. mfr_temperature_1_peak the mfr_temperature_1_peak command reports the highest temperature, in degrees celsius, reported by the read_temperature_1 measurement. this command is cleared using the mfr_clear_peaks command. this read-only command has two data bytes and is formatted in linear_5s_11s format. mfr_read_iin_peak the mfr_read_iin_peak command reports the highest current, in amperes, reported by the read_iin measurement. this command is cleared using the mfr_clear_peaks command. this command has two data bytes and is formatted in linear_5s_11s format. mfr_read_ichip the mfr_read_ichip command returns the measured input current, in amperes, used by the ltc3883. this command has two data bytes and is formatted in linear_5s_11s format. mfr_read_iin_chan the mfr_read_iin_chan command returns the calculated value of the input current, in amperes, as a function of read_iout and duty_cycle. for accurate values at low currents, the part must be in continuous conduction mode. if dcr sensing is used, the accuracy of the inductor dcr resistance, iout_cal_gain, will effect the accuracy of the mfr_read_iin command. this command has two data bytes and is formatted in linear_5s_11s format. mfr_temperature_2_peak the mfr_temperature_2_peak command reports the highest temperature, in degrees celsius, reported by the read_temperature_2 measurement. this command is cleared using the mfr_clear_peaks command. this read-only command has two data bytes and is formatted in linear_5s_11s format. pmb us c omman d de t ails
ltc3883/LTC3883-1 101 3883f nvm m emory c ommands store/restore command name cmd code description type format units nvm default value store_user_all 0x15 store user operating memory to eeprom. send byte na restore_user_all 0x16 restore user operating memory from eeprom. send byte na mfr_compare_user_all 0xf0 compares current command contents with nvm. send byte na store_user_all the store_user_all command instructs the pmbus device to copy the non-volatile user contents of the operating memory to the matching locations in the non-volatile user nvm memory. executing this command if the die temperature exceeds 85 c or is below 0 c is not recommended and the data retention of 10 years cannot be guaranteed. if the die temperature exceeds 130 c, the store_user_all command is disabled. the command is re-enabled when the ic temperature drops below 125c. communication with the ltc3883 and programming of the nvm can be initiated when vdd33 is available and vin is not applied. to enable the part in this state, using global address 0 x5b write mfr_ee_unlock to 0 x2b followed by 0xc4. the part can now be communicated with, and the project file updated. to write the updated project file to the nvm issue a store_user_all command. when vin is applied, a mfr_reset must be issued to allow the pw m to be enabled and valid adcs to be read. this write-only command has no data bytes. restore_user_all the restore_user_all command instructs the pmbus device to copy the contents of the non-volatile user memory to the matching locations in the operating memory. the values in the operating memory are overwritten by the value retrieved from the user commands. when a restore_user_all command is issued, the run pin and share_clk pin are asserted low until the restore is complete. the run pin and share_clk are then released. the rconfig resistor dividers are not re-read, and the value stored in nvm is used with the exception of the asel pin. the asel value read at power-up or when the part is reset is used to calculate the effective device address using the msb from nvm and the lsb based on the asel decode. store_user_all, mfr_compare_user_all and restore_user_all commands are disabled if the die exceeds 130c and are not re-enabled until the die temperature drops below 125c. this write-only command has no data bytes. mfr _compare_user_all the mfr_compare_user_all command instructs the pmbus device to compare current command contents with what is stored in non-volatile memory. if the compare operation detects differences, a cml bit 0 fault will be generated. this write-only command has no data bytes. pmb us c omman d de t ails
ltc3883/LTC3883-1 102 3883f fault logging command name cmd code description type d ata format units nvm default value mfr_fault_log 0xee fault log data bytes. this sequentially retrieved data is used to assemble a complete fault log. r block cf y na mfr_fault_log_ store 0xea command a transfer of the fault log from ram to eeprom. this causes the part to behave as if the pwm has faulted off. send byte na mfr_fault_log_clear 0xec initialize the eeprom block reserved for fault logging and clear any previous fault logging locks. send byte na mfr_fault_log the mfr_fault_log command allows the user to read the contents of the fault_log after the first fault occurrence since the last mfr_fault_log_clear command was last written. the contents of this command are stored in non- volatile memory, and are cleared by the mfr_fault_log_clear command. the length and content of this command are listed in table 11. if the user accesses the mfr_fault_log command and no fault log is present, the command will return a data length of 0. if a fault log is present, the mfr_fautl_log will return a block of data 147 bytes long. if a fault occurs within the first second of applying power, some of the earlier pages in the fault log may not contain valid data. note: the approximate transfer time for this command is 3.4ms using a 400khz clock. this read-only command is in block format. mfr_fault_log_store the mfr_fault_log_store command forces the fault log operation to be written to nvm just as if a fault event occurred. this command will set bit 3 of the status_mfr_specific fault if bit 7 enable fault logging is set in the mfr_config_all_ lt c 3883 command. if the die temperature exceeds 130 c, the mfr_fault_log_store command is disabled until the ic temperature drops below 125c. this write-only command has no data bytes. pmb us c omman d de t ails
ltc3883/LTC3883-1 103 3883f table 11. fault logging this table outlines the format of the block data from a read block data of the mfr_fault_log command. data format definitions lin 11 = pmbus = rev 1.1, part 2, section 7.1 lin 16 = pmbus rev 1.1, part 2, section 8. mantissa portion only byte = 8 bits interpreted per definition of this command d ata bits d ata format byte num block read command block length byte 147 the mfr_fault_log command is a fixed length of 147 bytes the block length will be zero if a data log event has not been captured header information fault position byte 0 indicates the fault that caused the fault log to be activated. mfr_real_time [7:0] byte 1 48 bit binary counter. the value is the time since the last reset in 200s increments. [15:8] byte 2 [23:16] byte 3 [31:24] byte 4 [39:32] byte 5 [47:40] byte 6 mfr_vout_peak [15:8] lin 16 7 peak read_vout since last mfr_clear_peaks command. [7:0] 8 reserved byte 9 reserved byte 10 mfr_iout_peak [15:8] lin 11 11 peak read_iout since last mfr_clear_peaks command. [7:0] 12 mfr_read_iin_chan_peak [15:8] lin 11 13 peak read_iin since last mfr_clear_peaks command. [7:0] 14 mfr_vin_peak [15:8] lin 11 15 peak read_vin since last mfr_clear_peaks command. [7:0] 16 read_temperature_1 [15:8] lin 11 17 external temperature during last event. [7:0] 18 reserved byte 19 always returns 0x00. reserved byte 20 always returns 0x00. read_temperature_2 [15:8] lin 11 21 internal temperature sensor during last event [7:0] 22 mfr_temperature_1_peak [15:8] lin 11 23 peak read_temperature _1 since last mfr_clear_peaks command . [7:0] 24 reser ved byte 25 always returns 0x00. reserved byte 26 always returns 0x00. cyclical d ata event n (data at which fault occurred; most recent data) event n represents one complete cycle of adc reads through the mux at time of fault. example: if the fault occurs when the adc is processing step 15, it will continue to take readings through step 25 and then store the header and all 6 event pages to eeprom read_vout [15:8] lin 16 27 [7:0] 28 reserved byte 29 always returns 0x00. reserved byte 30 always returns 0x00. read_iout [15:8] lin 11 31 [7:0] 32 pmb us c omman d de t ails
ltc3883/LTC3883-1 104 3883f mfr_read_iin_chan [15:8] lin 11 33 [7:0] 34 read_vin [15:8] lin 11 35 [7:0] 36 read_iin [15:8] lin 11 37 [7:0] 38 status_vout byte 39 reserved byte 40 always returns 0x00. status_word [15:8] word 41 [7:0] 42 mfr_read_ichip [15:8] word 43 mfr_read_ichip [7:0] 44 status_mfr_specific byte 45 reserved byte 46 always returns 0x00. event n-1 (data measured before fault was detected) read_vout [15:8] lin 16 47 [7:0] 48 reserved byte 49 always returns 0x00. reserved byte 50 always returns 0x00. read_iout [15:8] lin 11 51 [7:0] 52 mfr_read_iin_chan [15:8] lin 11 53 [7:0] 54 read_vin [15:8] lin 11 55 [7:0] 56 read_iin [15:8] lin 11 57 [7:0] 58 status_vout byte 59 reserved byte 60 always returns 0x00. status_word [15:8] word 61 [7:0] 62 reserved byte 63 always returns 0x00. reserved byte 64 always returns 0x00. status_mfr_specific byte 65 reserved byte 66 always returns 0x00. * * * event n-5 (oldest recorded data) read_vout [15:8] lin 16 127 [7:0] 128 reserved byte 129 always returns 0x00. reserved byte 130 always returns 0x00. read_iout [15:8] lin 11 131 [7:0] 132 pmb us c omman d de t ails
ltc3883/LTC3883-1 105 3883f mfr_read_iin_chan [15:8] lin 11 133 [7:0] 134 read_vin [15:8] lin 11 135 [7:0] 136 read_iin [15:8] lin 11 137 [7:0] 138 status_vout byte 139 reserved byte 140 always returns 0x00. status_word [15:8] word 141 [7:0] 142 reserved byte 143 always returns 0x00. reserved byte 144 always returns 0x00. status_mfr_specific byte 145 reserved byte 146 always returns 0x00. table 11a: explanation of position_fault values position_fault value source of fault log 0xff mfr_fault_log_store 0x00 ton_max_fault 0x01 vout_ov_fault 0x02 vout_uv_fault 0x03 iout_oc_fault 0x05 temp_ot_fault 0x06 temp_ut_fault 0x07 vin_ov_fault 0x0a mfr_temp_2_ot_fault mfr_fault_log_clear the mfr_fault_log_clear command will erase the fault log file stored values. it will also clear bit 3 in the status_mfr_specific command. after a clear is issued, the status can take up to 8ms to clear. this write-only command is send bytes. block memory write/read command name cmd code description type d ata format units nvm default value mfr_ee_unlock 0xbd unlock user eeprom for access by mfr_ee_erase and mfr_ee_ data commands. r/w byte reg na mfr_ee_erase 0xbe initialize user eeprom for bulk programming by mfr_ee_ data . r/w byte reg na mfr_ee_ data 0xbf data transferred to and from eeprom using sequential pmbus word reads or writes. supports bulk programming. r/w word reg na all the nvm commands are disabled if the die temperature exceeds 130 c. nvm commands are re-enabled when the die temperature drops below 125c. pmb us c omman d de t ails
ltc3883/LTC3883-1 106 3883f mfr_ee_unlock multiple writes to mfr_ee_unlock with the appropriate unlock keys are used to enable mfr_ee_erase and mfr_ ee_ data access and configure pec. communication with the ltc3883 and programming of the nvm can be initiated when vdd33 is applied and vin is not. to enable the part in this state, use global address 0 x5b command mfr_ee_unlock data 0 x2b followed by address 0x5b command mfr_ee_unlock data 0 xc4. when vin is applied, a mfr_reset must be issued to allow the pwm to be enabled and valid adcs to be read. writing 0 x2b followed by 0 xd4 clears pec, resets the eeprom address pointer and unlocks the part for eeprom erase and data command writes. writing 0 x2b followed by 0 xd5 sets the pec, resets the eeprom address pointer and unlocks the part for eeprom erase and data command writes. writing 0 x2b followed by 0 x91 and 0 xe4 clears pec, resets the eeprom address pointer and unlocks the part for eeprom data reads of all locations. writing 0 x2b followed by 0 x91 and 0 xe5 sets pec, resets the eeprom address pointer and unlocks the part for eeprom data reads of all locations. mfr _ee_erase a single write after the appropriate unlock key erases the eeprom allowing subsequent data writes. this command may be read to indicate if an eeprom access is in progress. a value of 0 x2b will erase the eeprom. if the part is busy writing or erasing the eeprom a non-zero value will be returned. mfr_ee_ data sequential writes or reads perform block loads or restores from the eeprom. successive mfr_ee_ data word writes will enter the eeprom until it is full. extra writes will lock the part. the first write is to the lowest address. the first read returns the 16 bit eeprom packing revision id. the second read returns the number of 16 bit words available. subsequent reads return eeprom data starting with the lowest address. pmb us c omman d de t ails
ltc3883/LTC3883-1 107 3883f typical a pplica t ions high efficiency 500khz 1.2v step-down converter with external v cc v in gnd 0.1f 1f 10f v in 6v to 14v 5v in 1f 5m 5k 100 6800pf 10k 22f 50v + d1 m1 m2 1k v out 1.2v 20a c out 530f 3883 ta06 10nf c out : 330h sanyo 4tpf330ml, 2 100f avx 12106d107kat2a d1: central cmdsh-3tr l: pulse pa 0515.321nlt 0.32h m1: infineon bsc032ne2ls m2: infineon bsc009ne2ls 1.0f 1.0f 0.22f 0.32h tg bg pgnd freq_cfg i in_sns boost v in_sns sync sw extv cc LTC3883-1 10k gpio 10k pgood 10k sda 10k pmbus interface v dd33 scl v out_cfg v trim_cfg asel wp i sense + i sense ? v sense + v sense ? v dd25 v dd33 tsns i th 10k alert 10k run 10k share_clk mmbt3906 10nf 10nf 10f 100 v dd25 20k 12.7k 24.9k 4.32k 10k 23.2k 20k 17.8k 1f 1k 3 high efficiency 500khz 2.5v step-down converter with sense resistor, no input current sense gnd 0.1f 1f 10f v in 6v to 24v 10k 4700pf 1000pf 30 6.81k 22f 50v 10f + d1 m1 m2 20k 12.7k 20k 17.8k 20k 15k v dd25 v out 2.5v 15a c out 530f 3883 ta04 10nf c out : 330h sanyo 4tpf330ml, 2 100f avx 12106d107kat2a d1: central cmdsh-3tr l: vishay ihlp4040dz01 0.56h m1: infineon bsc050n03lsg m2: infineon bsc011n03lsi 1.0f 1.0f 0.56h 0.002 tg bg pgnd freq_cfg i in_sns boost v in_sns sync wp sw intv cc ltc3883 10k gpio 10k pgood 10k sda 10k pmbus interface v dd33 scl v out_cfg v trim_cfg asel i sense + i sense ? v sense + v sense ? v dd25 v dd33 tsns i th 10k alert 10k run 5k share_clk mmbt3906 30 v in
ltc3883/LTC3883-1 108 3883f typical a pplica t ion s high efficiency 425khz 1v step-down converter with power block gnd 1f 10f v in 7v to 14v 1f 5m 10k 100 100 1000pf 100pf 5.62k 22f 50v + v out 1v 35a c out 530f 3883 ta05 c out : 330h sanyo 4tpf330ml, 2 100f avx 12106d107kat2a p1: vra001-4c3g acbel power block 1.0f 1.0f tg bg pgnd freq_cfg tsns i in_sns boost v in_sns v in sync sw wp intv cc ltc3883 10k gpio 10k pgood 10k sda 10k pmbus interface v dd33 scl v out_cfg v trim_cfg asel i sense + i sense ? v sense + v sense ? v dd25 v dd33 i th 10k alert 10k run 5k share_clk 1.2k 1f gnd v in p1 pwmh 7v gate drive pwml v gate v out cs ? cs + temp + temp ? 10nf 10f 10nf 24.9k 4.32k 20k 17.8k 16.2k 17.4k v dd25 3 0.22f
ltc3883/LTC3883-1 109 3883f high efficiency 500khz 2-phase 1.8v step-down converter with sense resistors typical a pplica t ion s gnd 0.1f 1f 10f v in 6v to 18v 1f 5m 5k 100 2200pf 1000pf 30 20k v dd25 4.99k 22f 50v + d1 m1 m2 c out1 530f 10nf c out1 , c out2 : 330h sanyo 4tpf330ml, 2 100f avx 12106d107kat2a d1, d2: central cmdsh-3tr l: vitec 59pr9875 0.4h m1, m3: infineon bsc050ne2ls m2, m4: infineon bsc010ne2lsi 1.0f 1.0f 0.4h 0.002 tg bg pgnd freq_cfg i in_sns boost v in_sns sync sw intv cc ltc3883 10k 10k pgood 10k sda 10k pmbus interface v dd33 scl v out_cfg v trim_cfg asel wp i sense + i sense ? v sense + v sense ? v dd25 v dd33 tsns i th 10k alert 10k run 10k share_clk mmbt3906 17.8k 24.9k 11.3k 30 v in gnd 0.1f 1f 10f 1f 5 100 1000pf 30 22f 50v + d2 m3 m4 c out2 530f 3883 ta07 v out 1.8v 40a 10nf 1.0f 1.0f 100pf 0.4h 0.002 tg bg pgnd freq_cfg i in_sns boost v in_sns sync sw intv cc ltc3883 sda scl v out_cfg v trim_cfg asel wp i sense + i sense ? v sense + v sense ? v dd25 v dd33 tsns i th alert run share_clk mmbt3906 30 100 100 pgood gpio pgood gpio 10nf 10nf 10f v in 10f 10nf 10nf 3 20k v dd25 15k 3
ltc3883/LTC3883-1 110 3883f typical a pplica t ion s high efficiency 3-phase 425khz 1.8v step-down converter with input current sense d1-d3: central cmdsh-3tr l0-l2: vishay ihlp-4040dz-11 0.56h m1, m3, m4: infineon bsc050ne2ls m2, m5, m6: infineon bsc010ne2lsi v in gnd 0.1f 1f 22f 10f 0.1f 1f 1f d3 d2 m3 m5 1f l1 0.56h 1.4k m4 m6 3883 ta08 10nf 10f 0.22f 0.22f 100pf 1.4k mmbt3906 l2 0.56h tg1 bg1 pgnd v dd25 v out0_cfg v out1_cfg v trim0_cfg v trim1_cfg asel boost1 v dd33 sync sw1 tg0 bg0 boost0 sw0 intv cc ltc3880 sda 1.4k scl alert gpio1 share_clk run1 tsns0 tsns1 i sense0 + i sense1 + v sense0 + v sense0 ? i sense0 ? i sense1 ? wp freq_cfg i th0 v sense1 run0 i th1 gpio0 v in gnd 0.1f 1f 10f v in 6v to 14v 1f 5m 5k 100 2200pf 4.99k 22f 50v + d1 m1 m2 v dd25 1.4k v out 1.8v 50a c out1 530f 10nf 1.0f 1.0f 0.22f l0 0.56h tg bg pgnd freq_cfg i in_sns boost v in_sns sync wp sw intv cc ltc3883 10k gpio 10k pgood 24.9k 11.3k 24.9k 11.3k 10k 15.8k 20k 17.8k 20k 17.8k 10k sda 10k pmbus interface scl v out_cfg v trim_cfg asel i sense + i sense ? v sense + v sense ? v dd25 v dd33 tsns i th 10k alert 10k run 10k share_clk mmbt3906 100 10nf 10nf 10f 1f 1.4k 1f 1.4k mmbt3906 + + c out3 530f c out2 530f c out1 , c out2 , c out3 : 330h sanyo 4tpf330ml, 2 100f avx 12106d107kat2a 3
ltc3883/LTC3883-1 111 3883f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion 5.00 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 31 1 2 32 bottom view?exposed pad 3.50 ref (4-sides) 3.45 0.10 3.45 0.10 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh32) qfn 0406 rev d 0.50 bsc 0.200 ref 0.00 ? 0.05 0.70 0.05 3.50 ref (4 sides) 4.10 0.05 5.50 0.05 0.25 0.05 package outline 0.50 bsc recommended solder pad layout apply solder mask to areas that are not soldered pin 1 notch r = 0.30 typ or 0.35 45 chamfer r = 0.05 typ 3.45 0.05 3.45 0.05 please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693 rev d)
ltc3883/LTC3883-1 112 3883f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2012 lt 0812 ? printed in usa r ela t e d p ar t s typical a pplica t ion this product has a license from powerone, inc. related to digital power technology as set forth in u.s. patent 7000125 and othe r related patents owned by powerone, inc. this license does not extend to standalone power supply products. high efficiency 500khz 1.8v step-down converter with dcr sense gnd 0.1f 1f 10nf 10nf 10f v in 6v to 24v 1f 5m 10k 100 2200pf 4.99k 22f 50v + d1 m1 m2 20k 12.7k 24.9k 9.09k 10k 23.2k 20k 17.8k 1.4k v dd25 1.4k v out 1.8v 20a c out 530f 0.22f 3883 ta02 100pf d1: central cmdsh-3tr l: vishay ihlp-4040dz-11 0.56h m1: infineon bsc050n03lsg m2: infineon bsc011n03lsi 1.0f 1.0f 0.56h tg bg pgnd freq_cfg i in_sns boost v in_sns v in pgood sw intv cc ltc3883 100 10k gpio 10k 10k sda 10k pmbus interface v dd33 scl v out_cfg v trim_cfg asel i sense + i sense ? v sense + v sense ? v dd25 v dd33 tsns i th 10k alert 10k run 5k share_clk wp sync mmbt3906 10f 1f c out : 330h sanyo 4tpf330ml, 2 100f avx 12106d107kat2a 3 part number description comments ltc3880/ltc3880-1 dual output multiphase step-down controller with digital power system management v in up to 24v, 0.5v v out 5.5v, analog control loop, i 2 c/pmbus, interface with eeprom and 16-bit adc ltc3866 sub milli-ohm current mode synchronous step-down controller with remote sense pll fixed frequency 250khz to 750khz, 4v v in 38v, 0.6v v out 5v, 4mm 4mm qfn-24, tssop-24e ltc3867 synchronous step-down controller with differential remote sense and nonlinear control pll fixed operating frequency 250khz to 750khz, 4v v in 38v, 0.6v v out 14v, 4mm 4mm qfn-24 ltc3833 fast accurate step-down controller with differential output sensing and up to 2mhz frequency very fast transient response, t on(min) = 20ns, 4.5v v in 38v, 0.6v v out 5.5v, tssop-20e, 3mm 4mm qfn-20 ltc3878/ltc3879 no r sense ? constant on-time synchronous step-down controller very fast transient response, t on(min) = 43ns, 4v v in 38v, 0.8v v out 0.9v in , ssop-16, msop-16e, 3mm 3mm qfn-16 ltc3775 high frequency synchronous voltage mode step-down controller fast transient response, t on(min) = 30ns, 4v v in 38v, 0.6v v out 0.8v in , msop-16e, 3mm 3mm qfn-16 ltc3861 dual, multiphase, synchronous step-down controller with diff amp and three-state output drive operates with power blocks, dr mos devices or external mosfet s, 3v v in 24v, up to 2.25mhz operating frequency ltc2978 octal, pmbus compliant power supply monitor supervisor, sequencer and margin controller fault logging to internal eprom, monitors eight output voltage channels and one input voltage

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